International business machines corporation (20240104277). SINGLE CORNER MIXED VOLTAGE NOISE IMPACT ON FUNCTION ANALYSIS simplified abstract

SINGLE CORNER MIXED VOLTAGE NOISE IMPACT ON FUNCTION ANALYSIS

Organization Name

international business machines corporation

Inventor(s)

Steven Joseph Kurtz of Austin TX (US)

Michael Henry Sitko of Jericho VT (US)

Rahul M. Rao of Bangalore (IN)

Sanjay Upreti of Lexington KY (US)

Ajith Kumar Madathil Chandrasekaran of Bangalore (IN)

SINGLE CORNER MIXED VOLTAGE NOISE IMPACT ON FUNCTION ANALYSIS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240104277 titled 'SINGLE CORNER MIXED VOLTAGE NOISE IMPACT ON FUNCTION ANALYSIS

Simplified Explanation

The patent application describes a method, system, and computer program product for implementing enhanced noise impact on function (NIOF) analysis of an IC design with nets in multiple different variable voltage domains next to each other. This involves modeling all multiple worst-case victim-aggressor voltage configurations in a single run leveraging noise abstracts characterized at a single voltage corner. The NIOF analysis accurately identifies incorrect victim switching or functional fails, provides design verification and the ability to sign-off an IC design with a single run, enables modifying an integrated circuit design to fix NIOF failures, and facilitates fabricating an integrated circuit.

• Method, system, and computer program product for enhanced NIOF analysis of an IC design
• Modeling multiple worst-case victim-aggressor voltage configurations in a single run
• Accurately identifying incorrect victim switching or functional fails
• Providing design verification and sign-off with a single run
• Enabling modification of IC design to fix NIOF failures
• Facilitating fabrication of an integrated circuit

Potential Applications

The technology can be applied in the semiconductor industry for IC design verification and fabrication processes.

Problems Solved

1. Accurate identification of incorrect victim switching or functional fails in IC designs 2. Efficient design verification and sign-off processes with a single run

Benefits

1. Improved accuracy in identifying design flaws 2. Time and cost savings in design verification 3. Enhanced efficiency in fixing design failures

Potential Commercial Applications

Optimizing IC design processes for improved reliability and performance.

Possible Prior Art

There may be prior art related to noise impact analysis in IC design, but specific examples are not provided in the patent application.

Unanswered Questions

== What is the specific technical process for modeling worst-case victim-aggressor voltage configurations in a single run? The patent application does not delve into the detailed technical steps involved in modeling multiple worst-case configurations.

== How does the NIOF analysis compare to traditional noise impact analysis methods in terms of accuracy and efficiency? The application does not provide a direct comparison between the NIOF analysis and traditional noise impact analysis methods.

Original Abstract Submitted

a method, system, and computer program product are disclosed for implementing enhanced noise impact on function (niof) analysis of an ic design having nets in multiple different variable voltage domains next to each other and modeling all multiple worst-case victim-aggressor voltage configurations in a single run leveraging noise abstracts characterized at a single voltage corner. the niof analysis enables accurately identifying incorrect victim switching or functional fails, effectively and efficiently providing design verification and the ability to sign-off an ic design with a single run, and enable modifying an integrated circuit design to fix niof failures, and fabricating an integrated circuit.