International business machines corporation (20240103967). Memory Decoder Providing Optimized Error Detection and Correction for Data Distributed Across Memory Channels simplified abstract

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Memory Decoder Providing Optimized Error Detection and Correction for Data Distributed Across Memory Channels

Organization Name

international business machines corporation

Inventor(s)

Barry M. Trager of Yorktown Heights NY (US)

Patrick James Meaney of Poughkeepsie NY (US)

Glenn David Gilda of Binghamton NY (US)

Lawrence Jones of Endwell NY (US)

Memory Decoder Providing Optimized Error Detection and Correction for Data Distributed Across Memory Channels - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240103967 titled 'Memory Decoder Providing Optimized Error Detection and Correction for Data Distributed Across Memory Channels

Simplified Explanation

The memory controller in this patent application decodes data blocks encoded by error correction code across multiple channels of a redundant memory system. It then generates a predicted channel mark to identify a likely source of data errors and corrects the data accordingly.

  • The memory controller decodes data blocks encoded by error correction code across multiple channels of a redundant memory system.
  • It generates a predicted channel mark based on tests of channel-induced syndromes to identify a likely source of data errors.
  • The memory controller corrects the data by re-reading and excluding data from the marked channel.

Potential Applications

This technology can be applied in:

  • Data storage systems
  • Communication systems
  • Information security systems

Problems Solved

This technology helps in:

  • Detecting and correcting data errors
  • Improving data reliability and integrity
  • Enhancing overall system performance

Benefits

The benefits of this technology include:

  • Increased data accuracy
  • Enhanced system reliability
  • Improved error correction capabilities

Potential Commercial Applications

This technology can be used in:

  • Data centers
  • Networking equipment
  • Storage devices

Possible Prior Art

One possible prior art for this technology is:

  • Error correction codes in memory systems

What are the limitations of this technology in real-world applications?

How does this technology compare to existing error correction methods in terms of efficiency and accuracy?

Original Abstract Submitted

a memory controller stores each of a plurality of data blocks encoded by error correction code (ecc) across multiple channels of a redundant memory system. based on receiving, from the memory system, channel data of a fetch operation requesting a data block, the memory controller decodes the channel data and concurrently generates a predicted channel mark based on tests of channel-induced syndromes generated from the channel data. the predicted channel mark identifies a marked channel among the multiple channels as a likely source of data errors. the memory controller determines whether the decoding detects an uncorrectable error in the channel data and, based on determining the decoding detects an uncorrectable error in the channel data, re-reads channel data corresponding to the data block and corrects the re-read channel data by excluding, from decoding, channel data received from the marked channel.