International business machines corporation (20240097006). GATE INDUCED DRAIN LEAKAGE REDUCTION IN FINFETS simplified abstract
Contents
- 1 GATE INDUCED DRAIN LEAKAGE REDUCTION IN FINFETS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 GATE INDUCED DRAIN LEAKAGE REDUCTION IN FINFETS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 How does this method compare to existing techniques for forming gate structures on semiconductor devices?
- 1.11 What are the specific performance improvements achieved by implementing this method in semiconductor device manufacturing?
- 1.12 Original Abstract Submitted
GATE INDUCED DRAIN LEAKAGE REDUCTION IN FINFETS
Organization Name
international business machines corporation
Inventor(s)
Alexander Reznicek of Troy NY (US)
Takashi Ando of Eastchester NY (US)
Jingyun Zhang of Albany NY (US)
Ruilong Xie of Niskayuna NY (US)
GATE INDUCED DRAIN LEAKAGE REDUCTION IN FINFETS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240097006 titled 'GATE INDUCED DRAIN LEAKAGE REDUCTION IN FINFETS
Simplified Explanation
The patent application describes a method of forming a semiconductor device with an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure present on a fin structure. The method includes removing the inner sidewall dielectric spacer, forming a channel epitaxial wrap around layer on the exposed portion of the fin structure, removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, and forming a functional gate structure within the gate opening.
- Formation of inner and outer dielectric spacers on a sacrificial gate structure on a fin structure
- Removal of inner sidewall dielectric spacer
- Formation of channel epitaxial wrap around layer on exposed fin structure
- Removal of sacrificial gate structure to provide gate opening to channel portion of fin structure
- Formation of functional gate structure within gate opening
Potential Applications
This technology can be applied in the manufacturing of advanced semiconductor devices, such as high-performance transistors.
Problems Solved
This technology helps in improving the performance and efficiency of semiconductor devices by providing a precise and controlled method of forming gate structures.
Benefits
The method allows for the creation of intricate semiconductor structures with enhanced functionality and performance.
Potential Commercial Applications
The technology can be utilized in the production of cutting-edge electronic devices, leading to advancements in the semiconductor industry.
Possible Prior Art
Prior art may include methods of forming gate structures on semiconductor devices using different spacer combinations and epitaxial layers.
Unanswered Questions
How does this method compare to existing techniques for forming gate structures on semiconductor devices?
The article does not provide a direct comparison with existing techniques, leaving the reader to wonder about the specific advantages and limitations of this new method.
What are the specific performance improvements achieved by implementing this method in semiconductor device manufacturing?
The article does not detail the exact performance enhancements resulting from the use of this method, leaving the reader curious about the specific benefits in terms of speed, power consumption, or other key metrics.
Original Abstract Submitted
a method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. the method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. the method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.
