International Business Machines Corporation patent applications published on September 28th, 2023

Summary of the patent applications from International Business Machines Corporation on September 28th, 2023

Recently, International Business Machines Corporation (IBM) has filed several patents related to various technologies. These patents cover a range of areas including memory structures, device creation methods, electronic heatsink safety systems, workload balancing methods, and sound analysis processors. Here is a summary of the patents filed by IBM:

- Patent 1: This patent describes a structure and method for creating a device with an inner electrode, an outer electrode, and a layer of phase change material. The method involves forming the electrodes on a substrate and adding the phase change material layer above them.

- Patent 2: This patent describes a structure and method for creating a device that includes a bottom electrode, a layer of phase change material, and an ovonic threshold switching layer. The layers are vertically aligned, and the method involves forming the layers in a specific order and surrounding them with a dielectric material.

- Patent 3: This patent describes a memory structure that uses a ReRAM module embedded in a substrate. The structure includes insulative and plasma-interacting components, and when exposed to plasma, a conductive filament is formed in the ReRAM module.

- Patent 4: This patent describes a type of MRAM cell that consists of different layers with angled sidewalls. The upper and lower sections have different components, and the tunnel barrier has angled side sections located on top of a second dielectric liner.

- Patent 5: This patent describes a system for electronic heatsink safety that includes a thermoelectric generator integrated into a heatsink. The generator produces a current based on the temperature difference between its parts, and this current activates an LED.

- Patent 6: This patent describes a high-density memory apparatus that consists of multiple transistors stacked vertically on top of each other. Each transistor has its own separate horizontal nanosheet and gate stack, and the nanosheets are connected to two-terminal memory units.

- Patent 7: This patent describes a system that includes a semiconductor structure with transistors located on the front end of a wafer and an MRAM cell placed on the backside. The MRAM cell is connected to the transistors through a contact on the backside of the wafer.

- Patent 8: This patent describes a method for collecting data from edge devices, predicting the travel path of a specific entity, and selecting an edge device based on proximity to the predicted path. A workload is then sent to the selected edge device.

- Patent 9: This patent describes a method for balancing the workload of processors in an eNodeB by transferring communication traffic to an underutilized core and putting it into sleep mode until needed again.

- Patent 10: This patent describes a processor that can analyze sound data, identify sound sources, generate simulations of the sound field, and modify the sound field within an environment based on user preferences.

• Notable applications:
• Creating devices with phase change material layers and electrodes
• Memory structures using ReRAM modules and MRAM cells
• Integrating thermoelectric generators into heatsinks for electronic safety
• High-density memory apparatus with vertically stacked transistors
• Balancing workload in wireless communication networks
• Sound analysis processors for modifying sound fields in specific environments.

Patent applications for International Business Machines Corporation on September 28th, 2023

EFFICIENT POWER TRANSFER TO ELECTRIC VEHICLES (17702338)

Inventor Kenichi Takasaki

Brief explanation

The abstract describes a method for determining the ability of a power transmission device to transfer electric charge in a specific area at a given time. This ability is based on a threshold number of vehicles that the device can charge efficiently. The abstract also explains how the predicted number of electric vehicles requesting charge in that area can be calculated and adjusted if it exceeds the threshold number of vehicles.

Abstract

An ability of a power transmission device to transfer electric charge in a power-transmission area at a particular point in time is identified. The ability comprises a threshold number of vehicles to which the power-transmission device can transfer electric charge with at least a threshold efficiency. A predicted number of electric vehicles that are likely to be requesting electric charge within the power-transmission area at the particular point in time is calculated. The number of electric vehicles that are likely to be requesting electric charge within the power-transmission area at the particular point in time is adjusted based on a determination that the predicted number of vehicles is not bound by the threshold number of vehicles.

AIR MEASUREMENT FOR GROUND VEHICLE NAVIGATION (17702922)

Inventor Shailendra Moyal

Brief explanation

This abstract describes a system for autonomous vehicles that can detect navigation instructions and communicate with multiple sensors to gather information about the vehicle's environment. If a sensor malfunctions, the system can identify the issue and use another sensor to measure the air quality near the vehicle. This air measurement is then used to direct the vehicle's movement in response to the navigation instruction.

Abstract

A navigation instruction of an autonomous vehicle is detected. The autonomous vehicle is in an environment. The autonomous vehicle is communicatively coupled to a plurality of sensors configured to capture environmental information of the environment. An anomalous sensor status of a first sensor of the plurality of sensors is determined based on the plurality of sensors. An air measurement is identified in response to the anomalous sensor status and based on a second sensor of the plurality of sensors. The air measurement is adjacent to the autonomous vehicle. Autonomous movement operation of the autonomous vehicle is directed in response to the movement instruction and based on the air measurement.

SMART AIR CONTROL IN A STORAGE SPACE (17656671)

Inventor Venkata Vara Prasad Karri

Brief explanation

This abstract describes a method where a processor receives data about the air quality in a smart environment that contains storage objects. The processor then uses this data to simulate the smart environment. It applies an optimization criteria to the simulation in order to improve the air condition level of the smart environment. Finally, the processor generates a design for the smart environment that meets the optimization criteria and improves the air quality.

Abstract

A processor may receive an air dataset associated with a smart environment having one or more storage objects. The processor may simulate the smart environment using the air dataset. The processor may apply an optimization criteria to the simulation of the smart environment. The processor may generate an optimum smart environment design associated with an improved air condition level of the smart environment and the optimization criteria.

COLLABORATIVE SOLAR POWER GENERATION (17655809)

Inventor Akash U. Dhoot

Brief explanation

This abstract describes a method, computer system, and computer program for generating solar power using a group of electric autonomous vehicles (EAVs). The system identifies the positions of the EAVs and their solar power generation capabilities. It then determines if any EAVs have a side that is not exposed to direct sunlight. If this is the case, the system calculates the direction and angle of the sunlight and instructs the EAVs to move collaboratively so that the sunlight is reflected from one EAV to another, allowing the unexposed EAV to receive sunlight and generate solar power.

Abstract

According to one embodiment, a method, computer system, and computer program product for solar power generation is provided. The embodiment may include identifying relative positions of co-located electric autonomous vehicles (EAVs) within a group. The embodiment may include identifying solar power generation metrics for each EAV. The embodiment may include determining whether at least two EAVs have a same side unexposed to direct sunlight. In response to determining at least two EAVs have a same side unexposed to direct sunlight, the embodiment may include identifying a direction and an angle of solar light impacting the group. Based on the relative positions and the direction and angle of solar light, the embodiment may include instructing a collaborative movement among the group such that solar light is reflected from an exterior surface of at least one EAV to an exterior surface of at least one other EAV which was unexposed to sunlight.

DYNAMIC CHANGING OF CONVEYOR PROFILE BASED ON RANGE OF ROBOT (17654413)

Inventor Sarbajit K. Rakshit

Brief explanation

This abstract describes a method, computer system, and computer program for robot assistance. The computer identifies the position of a robot and the range of movement of its arm in an environment. It then generates a plan to align a conveyor with the robot, ensuring that the conveyor can be engaged by the robot's arm within its range of movement. The conveyor and the robot have separate supports. The computer then transmits the alignment plan for execution, resulting in the movement of the conveyor according to the plan.

Abstract

A method, computer system, and a computer program product for robot assistance are provided. A computer identifies a position of a first robot in an environment and a range of movement of an arm of the first robot. The computer generates an alignment plan for moving a first conveyor to be aligned with the first robot so that the first conveyor is engageable with the arm of the first robot within the range of movement of the arm. The first conveyor and the first robot include respective supports that are separate from each other. The computer transmits the alignment plan for execution so that the first conveyor is moved according to the alignment plan.

MIGRATION OF PRIMARY AND SECONDARY STORAGE SYSTEMS (17655804)

Inventor David R. Blea

Brief explanation

The abstract describes a method for moving data from one storage system to another. The method involves receiving a command to migrate from the first storage system to the second storage system. The first storage system has a primary storage and a secondary storage, while the second storage system also has a primary storage and a secondary storage. In response to the command, data replication is initiated between the first primary storage and the second primary storage, as well as between the first primary storage and the second secondary storage. Finally, the migration from the first storage system to the second storage system takes place.

Abstract

Provided is a method for migrating from a first storage system to a second storage system. The method includes receiving a command to migrate from a first storage system to a second storage system, wherein the first storage system comprises a first primary storage and a first secondary storage, and wherein the second storage system comprises a second primary storage and a second secondary storage. The method further includes initiating, in response to receiving the command, data replication between the first primary storage and the second primary storage. The method further includes initiating, in response to receiving the command, data replication between the first primary storage and the second secondary storage. The method further includes migrating from the first storage system to the second storage system.

Automated Knowledge Graph Based Regression Scope Identification (17700905)

Inventor Yuan Li

Brief explanation

The abstract describes a mechanism for automatically identifying the scope of regression in a software product's requirements specification. It involves generating a knowledge graph of functional requirements and their corresponding code entities, and creating vector representations for both. By analyzing the similarity between these vector representations, the code entities are linked to the function entities. This process results in a regression scope knowledge graph that shows the relationships between the functional requirements and the existing code portions.

Abstract

Mechanisms are provided to automatically identify a regression scope of a requirements specification for at least one functionality of a software product. A first knowledge graph, having function entities, is generated of the requirements specification specifying functional requirements for a software product and a first vector representation is generated for the function entities. Code entities for existing code for the software product are generated that comprise features associated with portions of the existing code, and a second vector representation is generated for these code entities. Code entities are linked to function entities based on a vector similarity analysis between the first vector representation and the second vector representation. A regression scope knowledge graph output is generated, based on the linked code entities and function entities, that depicts relationships between function entities corresponding to the functional requirements with code entities corresponding to portions of existing code for the software product.

VARIABLE REPLACEMENT BY AN ARTIFICIAL INTELLIGENCE ACCELERATOR (17656358)

Inventor Cedric Lichtenau

Brief explanation

The abstract describes a system that replaces variables in a template artificial intelligence (AI) accelerator code with actual values. The system consists of a memory, a processor, and an AI accelerator with multiple engines. The processor computes a table of variables from the template code, and the AI accelerator generates a modified code by replacing the variables with real values from the table.

Abstract

A system for variable replacement in a template artificial intelligence (AI) accelerator code. The system includes: at least one memory; at least one processor communicatively coupled to the at least one memory, and configured for computing at least one table of variables from a template AI accelerator code; and an AI accelerator including a plurality of engines, and communicatively coupled to the at least one processor and the at least one memory. The AI accelerator is configured to create a variable replaced AI accelerator code for the plurality of engines of the AI accelerator from the template AI accelerator code by replacing variables in the template AI accelerator code with actual values from the at least one table of variables.

DEPLOYMENT OF SOFTWARE PROGRAMS BASED ON SECURITY LEVELS THEREOF (17656237)

Inventor Gianluca Volpe

Brief explanation

The abstract proposes a solution for deploying software programs by calculating a security indicator for each program based on the security indicators of its components. It suggests selecting a computing system for deployment based on a comparison between the program's security indicator and the system's security indicators. The abstract also mentions the proposal of a computer program, computer program product, and system for implementing this method.

Abstract

A solution is proposed for deploying software programs. A corresponding method comprises calculating a program security indicator of each software program according to corresponding component security indicators of software components being used by the software program. A computing system (or more) is selected for deploying the software program according to a comparison between the program security indicator and corresponding system security indicators of a plurality of available computing systems. A computer program and a computer program product for performing the method are also proposed. Moreover, a corresponding system is proposed.

SOFTWARE PACKAGE UPDATE HANDLING (17656245)

Inventor Ting Dai

Brief explanation

This abstract describes a method, system, and computer program for handling software package updates. The method involves installing an initial set of software packages in a virtual environment. A package dependency graph is then created to represent the independent and dependent software packages within the initial set. The method further includes updating one or more software packages with updated versions to generate a subsequent set of software packages. A compatibility check is performed on this subsequent set, and based on the results, an update prerequisite package is generated.

Abstract

A method, system, and computer program product for software package update handling are provided. The method installs an initial set of software packages in a virtual environment. A package dependency graph is generated representing independent software packages and dependent software packages of the initial set of software packages. One or more software packages are updated with one or more updated software packages to generate a subsequent set of software packages. A compatibility check is performed on the subsequent set of software packages. The method generates an update prerequisite package based on the compatibility check.

Efficient Data Layout and Alignment for Wide-Vector Accelerator Systems (17701308)

Inventor Shubham Jain

Brief explanation

The abstract describes techniques for efficiently processing AI workloads in wide-vector accelerator systems. These techniques involve dividing a data vector into segments and sub-segments, where each sub-segment contains words with data-bits. The data-bits are then physically mapped in a way that ensures words belonging to the same sub-segment are contiguous across all segments. This approach improves the execution of AI workloads in the accelerator system.

Abstract

Efficient data layout and alignment techniques for effectively executing AI workloads in wide-vector accelerator systems are provided. In one aspect, a method for processing AI workloads includes: logically dividing a data vector into a hierarchy of segments and sub-segments with each of the segments including more than one of the sub-segments, wherein each of the sub-segments includes words, and each of the words includes data-bits; and physically mapping the data-bits such that the words belonging to a same given one of the sub-segments are mapped contiguously across all of the segments. An AI accelerator system is also provided.

BRANCH PREDICTION USING SPECULATIVE INDEXING AND INTRALINE COUNT (17703063)

Inventor Brian Robert Prasky

Brief explanation

The abstract describes a method used in a processor to predict the direction of a branch instruction. When the processor encounters a branch instruction, it generates an index based on the instruction address, a global path vector (GPV), and a counter. This index is then used to select an entry from a data structure. The processor predicts the direction of the branch by using the information included in the selected entry. Additionally, the method may involve modifying a tag in the selected entry based on another GPV.

Abstract

A method of branch prediction in a processor includes: obtaining, by the processor, a branch instruction for which a direction of a branch is to be predicted; generating, by the processor, an index based on an instruction address, a global path vector (GPV), and a counter; selecting, by the processor, an entry from a data structure using the index; and predicting, by the processor, the direction of the branch using information included in the selected entry. The method may include modifying a tag in the selected entry based at least in part on another GPV.

REDUCING DOWNTIME CAUSED BY INCOMPATABILITY ISSUES FROM UPGRADING FIRMWARE AND SOFTWARE (17655839)

Inventor Anjil Reddy Chinnapatlolla

Brief explanation

The abstract describes a method and system for estimating the time required to update a virtualized computing system and reducing errors during the update process. The method involves identifying the updates needed by the system and comparing it to similar systems that have already been updated. By analyzing the performance characteristics of these similar systems and the time taken to update them, the system can project the time required to complete the update. Additionally, the method identifies any errors that occurred during the update of the similar systems and their corresponding resolutions. These error resolutions can then be applied proactively to the system being updated, potentially preventing similar errors from occurring.

Abstract

A method and system for estimating upgrade time and mitigating errors when updating a virtualized computing system. Operations of this method include, but are not necessarily limited to the following (and not necessarily in the following order): (i) identify updates needed by a system; (ii) compare the system to be updated to other systems to determine similar systems that already had the similar updates; (iii) project the time to complete the update based on the performance characteristics of the system to be updated, the performance characteristics of the similar systems that have already been updated, and the time taken to update the similar systems; (iv) identify errors that occurred when updating the similar systems and the corresponding error resolutions; and (v) pre-emptively apply configuration changes or other error resolutions to the system to be updated.

PROGRAMMING ELEMENTS ONTO A COMPUTATIONAL MEMORY (17656163)

Inventor Manuel Le Gallo-Bourdeau

Brief explanation

The abstract describes a method, device, and computer program for programming a computational memory. This memory can perform a computation task using a set of elements that encode another set of elements. The method involves carrying out the computation task using the computational memory and adjusting some of the elements based on the measured result of the task until the desired level of accuracy is achieved.

Abstract

Provided is a method, device, and computer program product for programming a set of first elements onto a computational memory. The computational memory allows for performing a computation task from a set of second elements that encode the set of first elements in the computational memory, respectively. The method includes performing the computation task by the computational memory using the set of second elements and adapting at least part of the set of second elements in the computational memory based on a measured result of the computation task, until the measured result of the computation task fulfils an accuracy condition.

INTELLIGENT WORKFLOW FOR END-OF-SUPPORT SOLUTION ADVISOR (17656689)

Inventor Melanie Dauber

Brief explanation

This abstract describes a method for predicting the best time to upgrade a computer system. The approach involves collecting real-time data from a user's device and comparing it to historical data to find similar devices. Based on this comparison, the system generates recommendations for the upgrade and schedules it at a time that aligns with these recommendations.

Abstract

In an approach for predicting an optimal system upgrade, a processor detects an upgrade is available for a system of a first user computing device. A processor gathers a set of live data from an environment of the first user computing device using a process mining software. A processor compares the set of live data to a set of historical data stored in a knowledge corpus to identify a second user computing device similar to the first user computing device. Responsive to identifying the second user computing device, a processor performs a pattern recognition to generate one or more critical recommendations associated with the upgrade for the system of the first user computing device. A processor schedules the upgrade for the system of the first user computing device during a period of time, wherein the period of time is scheduled consistent with the one or more critical recommendations.

EFFICIENT RECOVERY IN CONTINUOUS DATA PROTECTION ENVIRONMENTS (17656687)

Inventor UMESH DESHPANDE

Brief explanation

This abstract describes a computer-based method for efficiently selecting restore points in a continuous data protection environment. Restore points are specific points in time where data can be restored to in case of a system failure. The method involves receiving log entries that contain these restore points, identifying an interesting restore point, and grouping them based on factors like confidence score and restore time. These grouped restore points are then loaded onto available nodes in the data protection environment. A validation function is used to determine if the data corresponding to each restore point is valid, and any restore points with invalid data are discarded.

Abstract

A computer-implemented method, a computer system and a computer program product efficiently select restore points in a continuous data protection environment. The method includes receiving log entries that include restore points that correspond to data stored on nodes in the continuous data protection environment. The method also includes identifying an interesting restore point from the log entries. The method further includes grouping the interesting restore point for recovery based on one or more of a confidence score and a restore time. In addition, the method includes loading the group of interesting restore points on available nodes in the continuous data protection environment. The method also includes determining whether the data corresponding to each interesting restore point in the group is valid using a validation function. Lastly, the method includes discarding the interesting restore point when the data corresponding to the interesting restore point is not valid.

TASK-SPECIFIC LOGGING IN DIGITAL COMPUTER SYSTEMS (17656222)

Inventor Felix Beier

Brief explanation

This abstract describes a method for logging tasks in a computer system. When a task is executed in the computer system, it is logged into the system. The log records of the task include log metadata and log levels. The log metadata provides information about the task, while the log levels indicate the importance or severity of the task. 

Based on the execution log output of the task, the system determines the set of log metadata and log levels associated with it. This information is then used to determine the execution outputs of another task. Essentially, the system uses the logged information from previous tasks to guide the execution and logging of future tasks.

Abstract

A technique for logging tasks in a computer system. Tasks are logged into the computer system by executing at least one task at the computer system. A set of log metadata and a set of log levels of log records of the at least one task may be determined from an execution log output of the at least one task. Execution outputs of a further task may be determined according to the determined set of log metadata and associated set of log levels.

DETERMINATION OF A PRIORITIZED SUBSET OF TEST CASES TO RUN AFTER A SOURCE CODE CHANGE (17701542)

Inventor Chun Ling Li

Brief explanation

This abstract describes a computer-implemented method and a computer program product for updating source code with predetermined code pieces. The updated code segments will provide information about associated test cases when the test cases are executed. The method also involves running the test cases and, after making changes to the source code, determining a prioritized subset of the test cases to be executed. The computer program product contains instructions that enable a computer to perform this method.

Abstract

A computer-implemented method according to one embodiment includes updating code segments of source code to include predetermined code pieces. The updated code segments are configured to output information about associated test cases upon the test cases being run. The method further includes running the test cases, and subsequent to a change being made to the source code, determining a prioritized subset of the test cases. The prioritized subset of the test cases is run. A computer program product according to another embodiment includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and/or executable by a computer to cause the computer to perform the foregoing method.

FINAL CACHE DIRECTORY STATE INDICATION (17701777)

Inventor Jason D. Kohl

Brief explanation

This abstract describes a method for managing the designated authority status in a cache line. The designated authority (DA) member cache for a cache line is identified, and then the DA status is transferred from the initial DA member cache to a new DA member cache. The new DA member cache's activity is determined, and the final state of the initial DA cache is indicated based on the activity of the new DA member cache. The DA state in a cache control structure in a directory is overridden. Additionally, the abstract describes a method for managing cache accesses during a designated authority transfer. This involves receiving a DA status transfer request, receiving an indication that a first cache will invalidate its copy of the cache line, allowing a second cache to assume DA status for the cache line, and denying access to the first cache's copy of the cache line until the invalidation process is complete.

Abstract

A method for managing designated authority status in a cache line includes identifying an initial designated authority (DA) member cache for a cache line, transferring DA status from the initial DA member cache to a new DA member cache, determining whether the new DA member cache is active, indicating a final state of the initial DA cache responsive to determining that the new DA member cache is active, and overriding a DA state in a cache control structure in a directory. A method for managing cache accesses during a designated authority transfer includes receiving a designated authority (DA) status transfer request, receiving an indication that a first cache will invalidate its copy of the cache line, allowing a second cache to assume DA status for the cache line, and denying access to the first cache’s copy of the cache line until invalidation by the first cache is complete.

COLUMN BASED DATABASE LOCKS (17656068)

Inventor Shuo Li

Brief explanation

The abstract describes a technique for implementing locks in a relational database based on specific columns. Instead of locking the entire row, transactions can target specific columns of one or more records using primary keys. The locks on individual columns are stored separately for single keys and ranges of keys. When a certain number of columns for a record or range of records have been locked, these column locks can be combined into a single row-level lock. This helps reduce resource costs associated with maintaining multiple concurrent locks.

Abstract

Disclosed are techniques for relational database locks based on columns. Database transactions may be targeted to specific columns of one or more records, instead of the entire row for those records, using primary keys. Column locks on specific keys are stored separately than column locks on ranges of keys, which are both checked when requesting a new column lock for either a single key or a range of keys. When a threshold number of columns for a given record, or range of records/keys, have been locked, the column locks for that record, or range of records, can be combined into a single row level lock to reduce resource costs for maintaining multiple concurrent locks.

BLOCKCHAIN BASED MULTI VENDOR CHANGE MONITORING SYSTEM (17656010)

Inventor ADAM DALE BRAHAM

Brief explanation

This abstract describes a method, computer system, and computer program product for managing a multi-vendor environment. The system allows participants in the environment to request changes to an aggregate computer system. These requests are then processed by creating a change block and obtaining approval according to an endorsement policy. The approved change block is added to a distributed ledger for transparency and accountability. Additionally, the system monitors the performance of the aggregate computer system.

Abstract

A method, computer system, and a computer program product for managing a multi-vendor environment is provided. The present invention may include receiving a request to make a change to an aggregate computer system from a participant of the aggregate computer system. The present invention may include creating, in response to the request, a change block. The present invention may include receiving approval for the change block in accordance with an endorsement policy. The present invention may include adding the change block to a distributed ledger. The present invention may include monitoring a performance of the aggregate computer system.

Automatically Recommending Database Access Patterns for Transactions in Microservices (17655802)

Inventor Shivali Agarwal

Brief explanation

This abstract describes a method for recommending database access patterns for transactions in microservices. The goal is to improve the performance of microservices by optimizing access to data in database tables. The recommendation is generated by analyzing the field access graphs for the tables accessed by the transactions. The recommended database access pattern is then implemented based on user input and guidance on how to implement the recommended pattern.

Abstract

Recommending database access patterns for transactions in microservices is provided. A recommendation of a particular database access pattern to improve access by transactions to data in fields of tables in a database corresponding to a microservice is generated based on analysis of field access graphs for the tables accessed by the transactions. The recommendation of the particular database access pattern is output. The particular database access pattern is implemented to improve access by the transactions to the data in the fields of the tables in the database corresponding to the microservice to improve performance of the microservice based on user input and read view implementation guidance.

IDENTIFYING AND REPLACING LOGICALLY NEUTRAL PHRASES IN NATURAL LANGUAGE QUERIES FOR QUERY PROCESSING (17656690)

Inventor Octavian Popescu

Brief explanation

This abstract describes a method for identifying and replacing logically neutral phrases in natural language queries. The method involves receiving a natural language query and identifying both logically neutral and non-logically neutral anchors within the query. Boundaries containing logically neutral phrases are also identified. The method then detects semantic and logical relations between verbal phrases and functional language surrounding the anchors to reintroduce non-logically neutral language into the query. A modified query is generated by removing the boundaries and potentially replacing the logically neutral phrases. The modified query is then provided to a query processing system for further processing.

Abstract

An embodiment for identifying and replacing logically neutral phrases in natural language queries may include receiving a natural language query. The embodiment may also identify one or more logically neutral or non-logically neutral anchors in the natural language query. The embodiment may also identify boundaries containing one or more logically neutral phrases. The embodiment may further include detecting semantic and logical relations between verbal phrases and functional language between and adjacent to the one or more logically neutral and non-logically neutral anchors to reintroduce non-logically neutral language back into a non-logically neutral portion of the natural language query. The embodiment may also include generating a modified natural language query by automatically removing the boundaries and optionally replacing the one or more logically neutral phrases in the natural language query. The embodiment may further include providing the modified natural language query to a query processing system for further processing.

DATABASE QUERY PERFORMANCE IMPROVEMENT (17703453)

Inventor Hai Jun Shen

Brief explanation

This abstract describes an approach for improving the performance of statistical queries. The approach takes a set of structured query language (SQL) statements as input. It identifies parameters associated with these statements and creates a merged SQL statement by combining similar parameters. It then binds additional parameters to the merged statement. The approach generates a new SQL statement based on the merged one and also generates a remote SQL statement. Finally, it executes a commit statement on the remote SQL statement.

Abstract

An approach for optimizing statistical query performance. The approach receives a structured query language set. The approach identifies a first set of parameters associated with the statements of the SQL set. The approach creates a merged SQL statement based on one or more matching parameters of SQL statements in the SQL set. The approach binds a second set of parameters associated with the merged SQL statement to the merged SQL statement. The approach generates a SQL statement based on the merged SQL statement. The approach generates a remote SQL statement based on the SQL statement. The approach executes a commit statement on the remote SQL statement.

DESIGNING A FAIR MACHINE LEARNING MODEL THROUGH USER INTERACTION (17655803)

Inventor Oznur Alkan

Brief explanation

This abstract describes a computer-based method, program, and system for designing a fair machine learning model. The system allows a user to review biased subgroups in a dataset used for training the model and provides bias scores for these subgroups. If the user requests to mitigate the bias, the system preprocesses the dataset to reduce bias and retrain the model using the modified dataset. The system then presents the user with new bias scores for the subgroups in the updated dataset. The user can review these scores to determine if the fair machine learning model has been achieved.

Abstract

A computer-implemented method, a computer program product, and a computer system for designing a fair machine learning model through user interaction. A computer system receives from a user a request for reviewing one or more biased subgroups in a dataset used in training a machine learning model and presents to the user the one or more biased subgroups and respective bias scores thereof. A computer system preprocesses the dataset to mitigate bias, in response to receiving from the user a request for mitigating the bias associated with the one or more biased subgroups. A computer system retrains the machine learning model, using a new dataset obtained from preprocessing the dataset. A computer system presents to the user respective new bias scores of the one or more biased subgroups in the new dataset. The user reviews the respective new bias scores to determine whether the fair machine learning model is built.

TECHNOLOGY FOR PROVIDING PASSWORD SECURITY (17656551)

Inventor SALLY L HOWARD

Brief explanation

The abstract describes a technology that enhances password security by monitoring a text entry field. If a user enters the first part of their password into an inappropriate text field, the technology will delete or hide that portion to prevent unauthorized parties from seeing or intercepting it. The abstract also mentions the use of an integer value to determine the minimum number of characters required before the password text is deleted or obscured.

Abstract

Technology for password entry security that monitors a text entry field that is not an appropriate text entry field for password entry, and, on condition that a user enters a first portion of a designated user password into the text entry field, then machine logic deletes and/or obscures at least the first portion of the password from the text entry field so that it cannot be espied or intercepted by unauthorized parties. IN some embodiments, an integer number N is designated to determine how many characters must be in the first portion entered by the user before the password text is deleted or obscured.

USING TRAP CACHE SEGMENTS TO DETECT MALICIOUS PROCESSES (18325987)

Inventor Brian A. Rinaldi

Brief explanation

The abstract describes a computer program, system, and method that use trap cache segments to detect malicious processes. Trap cache segments are sections of the cache that are marked as traps for data in the storage. Other cache segments contain data from the storage but are not marked as trap cache segments. 

When a process in the computer system makes a memory function call to read data from a specific region of the memory device, the system checks if that region includes a trap cache segment. If it does, the memory function call is blocked, and the process is treated as potentially malicious.

In simpler terms, this technology helps identify and block potentially harmful processes by checking if they are trying to access certain marked sections of the computer's memory.

Abstract

Provided are a computer program product, system, and method for using trap cache segments to detect malicious processes. A trap cache segment to the cache for data in the storage and indicated as a trap cache segment. Cache segments are added to the cache having data from the storage that are not indicated as trap cache segments. A memory function call from a process executing in the computer system reads data from a region of a memory device to output the read data to a buffer of the memory device. A determination is made as to whether the region of the memory device includes the trap cache segment. The memory function call is blocked and the process is treated as a potentially malicious process in response to determining that the region includes the trap cache segment.

Federated Generative Models for Website Assessment (17655847)

Inventor Ambrish Rawat

Brief explanation

This abstract describes a method, computer program, and computer system that can predict and assess risks on websites. It does this by analyzing the user's past interactions with websites and simulating their actions on a specific target website. By simulating these actions, the system can identify potential risks on the target website. Once the risks are identified, the website can be updated to reduce or eliminate these risks.

Abstract

A method, computer program, and computer system are provided for predicting and assessing risks on websites. Data corresponding to historical interactions of a user with one or more websites is accessed. A simulation of actions of the user is generated based on the accessed data, and actions of the user are simulated on a pre-defined target website based on the generated simulation of the actions of the user. Risks on the target website are identified based on simulating the actions of the user. The website is updated to mitigate the identified risks.

GENERATING A POWER DELIVERY NETWORK BASED ON THE ROUTING OF SIGNAL WIRES WITHIN A CIRCUIT DESIGN (17656041)

Inventor David WOLPERT

Brief explanation

This abstract describes a method and device for creating an updated power delivery network for a circuit design. The power delivery network is determined based on the power characteristics of the circuit design's logic cells. It includes power wires and power staples that connect pairs of power wires. The method involves removing certain power staples from the network based on the power characteristics. After removing these staples, the signal wires for the logic cells are routed. This routing process includes placing the first signal wire in a routing track that corresponds to the removed power staples.

Abstract

Method and apparatus for generating an updated power delivery network. Generating the power delivery network includes determining power characteristics for a power delivery network of a circuit design based on logic cells of the circuit design. The power delivery network includes power wires and power staples connecting pairs of the power wires to each other. Further a first one or more of the power staples is remove from the power delivery network based on the power characteristics. Signal wires for the logic cells are routed after removing the first one or more of the power staples. Routing the signal wires includes routing a first signal wire of the signal wires in a routing track corresponding to the first one or more of the power staples.

SHORT NET PIN ALIGNMENT FOR ROUTING (17656364)

Inventor Hua XIANG

Brief explanation

This abstract describes a method for improving routing in a computer system. It involves aligning one or more short nets in a cell of an integrated circuit to execute a routing operation. A short net refers to a two-pin net with two gates on adjacent rows that are horizontally close together, within a certain threshold distance.

Abstract

Embodiments are provided for providing enhanced routing in a computing system by a processor. One or more of a plurality of short nets in a cell of an integrated circuit may be aligned for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold.

NATURAL LANGUAGE QUESTION ANSWERING USING NON-RELATIONAL TABLES (17656487)

Inventor Vishwajeet Kumar

Brief explanation

This abstract describes a question answering bot that can understand and analyze non-relational data tables. The bot uses natural language processing (NLP) to extract key features from a question about the data table. It then identifies similar features in the data table itself. Based on these features, the bot determines relevant cells in the data table and provides an answer to the question using the information from those cells.

Abstract

A question answering bot that digests non-relational data tables is provided. A processor receives a question regarding a non-relational data table. A processor extracts at least one feature of the question using a natural language processing (NLP) model. A processor extracts at least one similar feature of the non-relational data table to the extracted at least one feature of the question. A processor determines at least one relevant cell in the non-relational data table based on the at least one feature of the question and the at least one similar feature of the non-relational data table. A processor provides an answer to the question, where the answer is based on the at least one relevant cell.

GENERATING SEMANTIC VECTOR REPRESENTATION OF NATURAL LANGUAGE DATA (17656418)

Inventor Thanh Lam Hoang

Brief explanation

This abstract describes a computer-based method for automatically generating a semantic vector representation of a relationship between a specific group of entities in natural language text. The method involves parsing the text segment into an abstract meaning representation (AMR) graph, which represents the entities. The method then extracts minimum Steiner trees from the AMR graph, which are subgraphs that connect the nodes representing the entities with the fewest edges. A graph neural network (GNN) is trained to determine vector embeddings for these minimum Steiner trees. Finally, the vector embeddings are aggregated to create a semantic vector representation of the relationship between the specific group of entities.

Abstract

A computer-implemented method for automatically generating a semantic vector representation of a relation between a specific set of entities in natural language text is provided. The method may include, in response to receiving a text segment comprising a set of entities, automatically parsing the text segment into an abstract meaning representation (AMR) graph comprising nodes representing the set of entities. The method may further include extracting a number of minimum Steiner trees from the AMR graph, and wherein each Steiner tree comprises a minimum amount of edges between the nodes corresponding to a first entity and at least one second entity. The method may further include using a trained graph neural network (GNN) to determine vector embeddings for the minimum Steiner trees. The method may further include aggregating the vector embeddings to generate the semantic vector representation of the relation between the specific set of entities.

MINING ASYNCHRONOUS SUPPORT CONVERSATION USING ATTRIBUTED DIRECTLY FOLLOWS GRAPHING (17655875)

Inventor SAMPATH DECHU

Brief explanation

The abstract describes a computer-based method, system, and program for analyzing asynchronous support conversations using a technique called attributed directly follows graphing. The method involves collecting conversation threads from a data stream, labeling each utterance with an event label, analyzing these labels, and generating an attributed directly follows graph based on the analysis.

Abstract

Provided is a computer-implemented method, system, and computer program product for process mining asynchronous support conversations using attributed directly follows graphing. A processor may collect a plurality of conversation threads from an asynchronous data stream. The processor may label each utterance of a plurality of utterances from the plurality of conversation threads with an event label. The processor may analyze the event label for each utterance of the plurality of utterances. The processor may generate, based on the analyzing of the event label for each utterance, an attributed directly follows graph (DFG).

IDENTIFY AND AVOID OVERFLOW DURING MACHINE LEARNING (ML) INFERENCE WITH HOMOMORPHIC ENCRYPTION (17656290)

Inventor LEV GREENBERG

Brief explanation

The abstract discusses the problem of identifying and preventing overflow events in machine learning inference operations when using homomorphic encryption. It suggests creating an initial overflow event to determine the achieved values, which are then compared to selected encryption libraries. This comparison helps adjust the parameters of the machine learning inference operation to avoid future overflow events during subsequent runs.

Abstract

Identifying and avoiding an overflow event while performing machine learning inference operations with homomorphic encryption. Prior to a first run of a machine learning inference operation, a first overflow event is created in order to determine the values that are achieved values. These values are compared to a set of user selected homomorphic encryption libraries in order to determine which parameters of the machine learning inference operation must be adjusted in order to avoid future overflow events during subsequent runs of the machine learning inference operation.

MULTI-LEVEL COORDINATED INTERNET OF THINGS ARTIFICIAL INTELLIGENCE (17705873)

Inventor Aaron K. Baughman

Brief explanation

The abstract describes a process in which machine learning operations are performed on input data from Internet of Things devices. These operations are performed in multiple levels or stages of machine learning. The outputs from each level are used as inputs for the next level. Finally, an output specific to the Internet of Things is identified at the last level of machine learning.

Abstract

A first plurality of machine learning operations are performed on Internet of Things (IoT) input data in an IoT ecosystem. The first plurality of machine learning operations are performed using a first machine learning level. One or more first machine learning outputs are received from the first machine learning level. A second plurality of machine learning operations are executed on the one or more first machine learning outputs. The second plurality of machine learning operations are executed using a second machine learning level. One or more second machine learning outputs are obtained from the second machine learning level. A third plurality of machine learning operations run on the one or more second machine learning outputs. The third plurality of machine learning operations run using a third machine learning level. An IoT output is identified from the third machine learning level.

HARDWARE IMPLEMENTATION OF ACTIVATION FUNCTIONS (17701809)

Inventor Stefano Ambrogio

Brief explanation

The abstract describes a device that uses a circuit to implement a non-linear activation function. This circuit includes a comparator, a capacitor, and a ramp voltage generator. The capacitor stores an input voltage that corresponds to the input value of the activation function. The ramp voltage generator generates a ramp voltage that is compared to the stored input voltage by the comparator during a conversion period. Based on the result of this comparison, the comparator generates a voltage pulse with a duration that encodes the activation output value of the non-linear activation function based on the input value.

Abstract

A device comprises activation function circuitry configured to implement a non-linear activation function. The activation function circuitry comprises a comparator circuit, a capacitor, and a ramp voltage generator circuit. The capacitor comprises a terminal coupled to a first input terminal of the comparator circuit, and is configured to receive and store an input voltage which corresponds to an input value to the non-linear activation function. The ramp voltage generator circuit is configured to generate a ramp voltage which is applied to a second input terminal of the comparator circuit. The comparator circuit is configured to compare, during a conversion period, the stored input voltage to the ramp voltage, and generate a voltage pulse based on a result of the comparing. The voltage pulse comprises a pulse duration which encodes an activation output value of the non-linear activation function based on the input value to the non-linear activation function.

CALIBRATING ANALOG RESISTIVE PROCESSING UNIT SYSTEM (17704515)

Inventor Stefano Ambrogio

Brief explanation

The abstract describes a system that includes a processor and a resistive processing unit (RPU) array. The RPU array consists of cells that contain programmable resistive memory devices used to store weight values. The processor is designed to obtain a matrix of target weight values and program the cells in the RPU array to store weight values corresponding to the target values. The system then performs a calibration process to adjust the RPU array. This process involves iteratively adjusting the target weight values in the matrix and reprogramming the stored weight values in the RPU array based on the adjusted target values. The goal of the calibration process is to reduce variation in the output lines of the RPU array when generating and outputting multiply-and-accumulate distribution data.

Abstract

A system comprises a processor, and a resistive processing unit (RPU) array. The RPU array comprises an array of cells which respectively comprise resistive memory devices that are programable to store weight values. The processor is configured to obtain a matrix comprising target weight values, program cells of the array of cells to store weight values in the RPU array, which correspond to respective target weight values of the matrix, and perform a calibration process to calibrate the RPU array. The calibration process comprises iteratively adjusting the target weight values of the matrix, and reprogramming the stored weight values of the matrix in the RPU array based on the respective adjusted target weight values, to reduce a variation between output lines of the RPU array with respect to multiply-and-accumulate distribution data that is generated and output from respective output lines of the RPU array during the calibration process.

GENERATING AND MANAGING DEEP TENSOR NEURAL NETWORKS (17938131)

Inventor Lior Horesh

Brief explanation

The abstract describes techniques for creating and managing deep tensor neural networks. These networks consist of nodes connected by weighted edges, and a network management component is responsible for extracting features from input data and evolving the data based on predefined rules. The network uses non-linear activation functions to process the data and generate output. The management component also trains the network by comparing its output to simulated output and making updates to the network based on a defined loss function. These updates involve adjusting the weights and biases of the network using tensor operations.

Abstract

Techniques for generating and managing, including simulating and training, deep tensor neural networks are presented. A deep tensor neural network comprises a graph of nodes connected via weighted edges. A network management component (NMC) extracts features from tensor-formatted input data based on tensor-formatted parameters. NMC evolves tensor-formatted input data based on a defined tensor-tensor layer evolution rule, the network generating output data based on evolution of the tensor-formatted input data. The network is activated by non-linear activation functions, wherein the weighted edges and non-linear activation functions operate, based on tensor-tensor functions, to evolve tensor-formatted input data. NMC trains the network based on tensor-formatted training data, comparing output training data output from the network to simulated output data, based on a defined loss function, to determine an update. NMC updates the network, including weight and bias parameters, based on the update, by application of tensor-tensor operations.

REDUCING COMPUTATIONAL REQUIREMENTS FOR MACHINE LEARNING MODEL EXPLAINABILITY (17701911)

Inventor Stefan A. G. Van Der Stockt

Brief explanation

The abstract describes a process where a first input transaction is classified into a specific input space cluster. This cluster is then mapped to a single explainability space cluster. Using an interpretable model associated with this explainability space cluster, the prediction made by a machine learning model for the first input transaction is explained.

Abstract

A first input transaction is classified into a first input space cluster in a set of input space clusters. It is determined that the first input space cluster maps to a single explainability space cluster in a set of explainability space clusters. Using an interpretable model corresponding to the single explainability space cluster, a first machine learning model prediction is explained, the first machine learning model prediction resulting from processing, by a machine learning model, the first input transaction.

COGNITIVE USABILITY TEST (17701902)

Inventor Yue Dong

Brief explanation

The abstract describes a system that includes a memory and a processor. The processor is responsible for performing various operations. These operations involve training a cognitive engine and receiving a goal for the cognitive engine. The cognitive engine is then used to recognize actionable elements and perform operations on them. The system also tracks data related to these operations and generates a usability score for a user based on this data.

Abstract

A system may include a memory and a processor in communication with the memory. The processor may be configured to perform operations. The operations may include training a cognitive engine and receiving a goal for the cognitive engine. The operations may include recognizing, with the cognitive engine, at least one actionable element and attempting, with the cognitive engine, operations on the at least one actionable element. The operations may include tracking data affiliated with the operations and generating, based on the data, a usability score for a user.

STABLE LOCAL INTERPRETABLE MODEL FOR PREDICTION (17699613)

Inventor Xiao Ming Ma

Brief explanation

The abstract describes a computer-based method for machine learning. It involves determining the appropriate size of a kernel for the model, creating a local interpretable linear model using this kernel size, and calculating the contribution and confidence of a specific feature in the model. The method also includes updating the model to generate a final version and computing an overall confidence score for this final model.

Abstract

Examples described herein provide a computer-implemented method that includes determining a kernel width for the machine learning model. The method further includes building a local interpretable linear model using the kernel width. The method further includes computing a contribution and confidence for a feature of the local interpretable linear model. The method further includes updating the local interpretable linear model to generate a final model and computing an overall confidence for the final model.

Computer Technology For Setting And Presenting An Itinerary For A Traveler (17656755)

Inventor Venkata Vara Prasad Karri

Brief explanation

The abstract describes computer technology that uses crowd sourced data to create personalized itineraries based on a person's interests, experience scores, weather conditions, and other relevant factors. It also includes technology for filtering and stitching together images to suggest a personalized route based on a person's preferences.

Abstract

Computer technology for leveraging crowd sourced data to create an experience scoring based itinerary that outputs an itinerary of POI's (points of interest) based on relevancy to the person's interest, scoring experience, weather conditions and other factors relevant to setting the destinations, order and/or scheduling of the traveler's itinerary (for example, a daily schedule for a family on holiday). Also, computer technology for filtration of a set of images unique to a person's profile and taste and stitching these images to suggest a personalized route specific to that person's understanding.

ARTIFICIAL INTELLIGENCE-BASED TASK ASSIGNMENT ASSISTANT IN MULTIPARTICIPANT MESSAGE EXCHANGES (17656355)

Inventor Jonathan Terner

Brief explanation

The abstract describes a system that automatically assigns tasks in a group messaging setting. It does this by analyzing the messages exchanged between participants and identifying tasks that need to be completed. The system then determines a task leader and criteria for the tasks. It uses a database of past task completions to find potential candidates for completing the tasks and assigns a likelihood to each candidate. Based on this likelihood, a list of ranked candidates is generated and presented to the task leader. The task leader selects at least one candidate from the list, and the system automatically notifies the selected candidate of the tasks. The system also updates its database of past task completions.

Abstract

Automatic task assignment in a multiparticipant message exchange includes receiving, by a computer, data snapshots from a collaborative message exchange between one or more participants. Based on the data snapshots, the computer identifies tasks requiring completion, a task leader among participants, and a task criteria. Based on a semantic match between the task criteria and a database of historical task completion, the computer identifies a candidate pool for completing the tasks and determines a likelihood of each candidate completing the tasks. A relevancy score is assigned based on the likelihood and used to generate a list of ranked candidates for completing the tasks. The computer presents the list to the task leader, receives a selection from the task leader including at least one candidate for completing the tasks, automatically notifies the selected candidate of the tasks to be completed, and updates the database of historical task completion.

TECHNIQUES FOR DISCOVERING AND SHARING DIGITAL WORKFLOW TASK ASSIGNMENTS (17653500)

Inventor Peng Hui Jiang

Brief explanation

This abstract describes a method, computer system, and computer program for task management. The invention involves analyzing the requirements of a new task to be performed by a computer, determining if other tasks can be performed simultaneously with the new task, identifying potential candidates to perform the new task, creating a workflow for all simultaneous tasks, and mapping the tasks to the candidates. The invention also involves evaluating the skillset and availability of the candidates for performing the simultaneous tasks and generating a confidence rating for each candidate based on their skillset, availability, and the workflow.

Abstract

A method, computer system, and a computer program product for task management is provided. The present invention may include analyzing task requirements for a new task to be performed by a computer. The present invention may include determining when other tasks are to be performed at least partially simultaneously with said new task. The present invention may include determining one or more candidates engageable to perform said new task. The present invention may include generating a workflow for all tasks that are to be performed simultaneously and mapping said tasks with said engageable candidate task performer(s). The present invention may include determining skillset and availability of said one or more engageable candidates for performing said simultaneous tasks, said simultaneous tasks including said new task, and generating a confidence rating for each of said candidate task performers by analyzing said workflow and said candidate’s skillset, and availability for each simultaneous task.

AUTOMATIC MACHINE ASSEMBLY GUIDANCE (17656229)

Inventor Venkata Vara Prasad Karri

Brief explanation

This abstract describes a process where a processor receives data about the components of a machine and uses that data to create a digital twin of the machine. The digital twin is then simulated, and based on the simulation results, an optimized assembly plan for the machine is generated.

Abstract

A processor may receive component data associated with the machine. The component data may be associated one or more machine auxiliary components configured within one or more environments. The processor may generate a digital twin associated with the machine. The digital twin associated with the machine area may be based, at least in part, on the component data. The processor may simulate the digital twin of the machine. The processor may generate, responsive to simulating the digital twin associated with the machine, the optimized assembly plan for the machine.

RISK REDUCTION OPTIMIZATION IN A SMART ENVIRONMENT (17656227)

Inventor Venkata Vara Prasad Karri

Brief explanation

This abstract describes a system where a processor receives data about workers in a smart environment. The processor then creates a digital replica of the environment based on this data. The processor can simulate this digital twin and determine a safety score associated with the workers.

Abstract

A processor may receive worker data associated with a smart environment having one or more workers. The processor may generate a digital twin of the smart environment. The digital twin may be based, at least in part, on the worker data. The processor may simulate the digital twin of the smart environment. The processor may identify, responsive to simulating, a safety score. The safety score may be associated with the one or more workers.

DATA CENTER GUIDE CREATION FOR AUGMENTED REALITY HEADSETS (17656309)

Inventor Rodolfo Lopez

Brief explanation

This abstract describes a method, computer program, and computer system that automatically generates augmented reality-based guides for maintenance procedures. The system retrieves text instructions for performing maintenance on a device in a data center. It then extracts imperative statements from the instructions and identifies named entities within those statements. The system generates a mapping of the named entity's position on the device within the data center. This mapping is provided to an augmented reality device, which displays the extracted imperative statement and the mapping to the user. Essentially, this technology helps users perform maintenance procedures by providing visual guidance through augmented reality.

Abstract

A method, computer program product and computer system to automatically generate augment reality-based guides for maintenance procedures is provided. A processor retrieves non-structured text instructions to perform a maintenance procedure on a device within a data center. A processor extracts at least one imperative statement from the non-structured text instructions. A processor identifies a named entity in the extracted at least one imperative statement from the non-structured text instructions. A processor generates a mapping of the named entity to be used by an augmented reality device, where the mapping indicates the position of the named entity on the device within a data center. A processor provides to the augmented reality device the extracted at least one imperative statement and the mapping of the named entity, where the augmented reality device displays the extracted imperative statement and the mapping of the named entity to a user of the augmented reality device.

DOCKET CREDENTIAL INSERTION IN NON-FUNGIBLE TOKENS (17656035)

Inventor Nitin Gaur

Brief explanation

In simple terms, the abstract is describing a process in a blockchain network where a node creates a unique digital token called a non-fungible token (NFT). This NFT is associated with certain transfer conditions. The node also creates a document called a docket credential that includes the transfer terms for the NFT. This docket credential is then used as part of a signature scheme for the NFT. Finally, the node adds the signed NFT block to the blockchain network.

Abstract

A node in a blockchain network generates a non-fungible token (NFT) and obtain docket information for the NFT comprising transfer conditions for the NFT. The node also generates a docket credential with embedded transfer terms for the NFT from the docket information as part of a signature scheme for the NFT and signs an NFT block on a blockchain network with the docket credential.

DIGITAL ARTIFACT MARKETPLACE (17656233)

Inventor Vasileios Vasileiadis

Brief explanation

This abstract describes a method for storing, searching, acquiring, and combining digital artifacts. A digital artifact is a collection of digital data with provenance and usage information. The method involves obtaining the digital artifact from a digital marketplace platform, transforming it to define access privileges, and sharing it in the platform's catalog. Usage requests are authorized based on these access privileges, and the source of the digital artifact is rewarded based on its usage.

Abstract

In an approach for storage, search, acquisition, and composition of a digital artifact, a processor obtains the digital artifact in a digital marketplace platform. The digital artifact is a collection of digital data with automatically generated and verifiable provenance and usage data. A processor transforms the digital artifact to define an access privilege. A processor shares the digital artifact in the digital marketplace platform by providing a view of a catalogue including the digital artifact. A processor authorizes a usage request based on the access privilege. A processor rewards a source of the digital artifact based on the usage of the digital artifact.

DIGITAL CREDENTIAL DEPENDENCY MANAGEMENT (17648828)

Inventor Milan Saumil Patel

Brief explanation

This abstract describes techniques for managing digital credentials and their dependencies. It explains that metadata mappings are used to keep track of the attributes of digital credentials and the entities that rely on them. When a digital credential is presented for verification, a mapping is created between the verifying entity and the requested attributes. Any updates to the digital credentials or their attributes can trigger automatic notifications to the verifying entities listed in the mapping. The content and recipients of these notifications can be customized based on user settings.

Abstract

Disclosed are techniques directed to digital credential dependency management. Metadata mappings are maintained between digital credentials, their underlying attributes, and dependent entities which verify and rely upon the digital credentials. When a digital credential is presented for proof to a verification entity, a dependency mapping is generated linking between the verification entity and the attributes that the verification entity requested for presentation. Updates to the digital credentials, or underlying attributes of the digital credentials, can trigger automatic notifications to the verification entities indicated in the dependency mapping. Automatic notifications, as well as their contents, may be defined by user settings to dictate which verification entities receive notifications and what digital credential and underlying attribute information is included in said notifications.

MITIGATING COMPRESSION INDUCED LOSS OF INFORMATION IN TRANSMITTED IMAGES (17656013)

Inventor Andrew Jason Lavery

Brief explanation

The abstract describes a method to prevent loss of information in images during electronic transmission. It involves using a computer vision model to extract important data points from the image, such as the name of a medicine or dosage instructions. A test transmission image is then created by applying compression operations to a copy of the image, and the same data extraction process is repeated. Any differences in the extracted data points are used to modify the image before transmission, ensuring that important information is not lost.

Abstract

Disclosed are techniques for mitigating loss of information in electronically transmitted images caused by compression operations performed on the images to facilitate transmissions. When an image for electronic transmission is received, a computer vision model extracts various points of data from the image corresponding to information present in the image that is intended for human consumption (for example, in a scan of a handwritten note from a doctor prescribing a medicine for a patient, some of the data points may include the name of the medicine, the dosage value, and when the medicine should be consumed). A test transmission image is then generated by applying the compression operations which are applied in the electronic transmission to a copy of the image, and that copy is also inputted to the computer vision model for data point extraction. Differences in the extracted data points are used to modify the image for transmission.

MIXED REALITY BASED CONTEXTUAL EVALUATION OF OBJECT DIMENSIONS (17654421)

Inventor SHEFALI BANSAL

Brief explanation

This abstract describes a processor that can analyze a specific area and identify objects within it. The processor then evaluates each object by measuring it and determining its purpose. Based on this evaluation, the processor generates a suggested placement for each object.

Abstract

A processor may analyze a target area. The processor may identify, from the analyzing, one or more objects in the target area. The processor may evaluate each of the one or more objects in the target area. Evaluating each of the one or more objects may include measuring each of the one or more objects and determining a purpose for each of the one or more objects. The processor may generate, based on the evaluating, a placement for each of the one or more objects.

MACHINE LEARNING MODELS TRAINED FOR MULTIPLE VISUAL DOMAINS USING CONTRASTIVE SELF-SUPERVISED TRAINING AND BRIDGE DOMAIN (17705597)

Inventor Leonid KARLINSKY

Brief explanation

The abstract describes a system that uses a processor to train a neural network model. The processor receives both the model and a set of training images. The training images are converted into transformed images within a bridge domain using a bridge transform. The model is then trained using a contrastive loss, which helps generate representations based on the transformed images.

Abstract

An example a system includes a processor to receive a model that is a neural network and a number of training images. The processor can train the model using a bridge transform that converts the training images into a set of transformed images within a bridge domain. The model is trained using a contrastive loss to generate representations based on the transformed images.

OBJECT-CENTRIC AND RELATION-CENTRIC GRAPH NEURAL NETWORKS FOR PHYSICAL PROPERTY DISCOVERY (17656296)

Inventor Zhenfang Chen

Brief explanation

This abstract describes a method, computer system, and computer program that can identify the intrinsic physical properties of objects. It involves identifying objects in a video set, extracting observable physical properties such as trajectories, and using a property-based graph neural network to infer the intrinsic properties of the objects based on these trajectories.

Abstract

According to one embodiment, a method, computer system, and computer program product for identifying one or more intrinsic physical properties of one or more objects is provided. The present invention may include identifying one or more objects in a video set, extracting observable physical properties of the identified one or more objects from the video set, including one or more trajectories, and inferring, by a property-based graph neural network, intrinsic properties of the one or more objects based on the trajectories.

AUDIO/VIDEO (A/V) FUNCTIONALITY VERIFICATION (17656435)

Inventor Yara Rizk

Brief explanation

The abstract describes a method for verifying the functionality of audio/video streams in a web-based conference. It involves capturing a segment of the video feed before it is transmitted over a network and storing it. Similarly, a segment of the video feed is captured after transmission and stored. These two segments are then compared to determine the quality of the video feed.

Abstract

Aspects of the present disclosure relate to audio/video (A/V) stream functionality verification. A stream segment of a video feed prior to transmission over a network as captured by a transmitting device within a web-based conference can be stored. A stream segment of the video feed after transmission over the network as received by a receiving device within the web-based conference can be stored. The stream segment of the video feed prior to transmission over the network can be compared with the stream segment of the video feed after transmission over the network to determine a video feed quality.

TOPIC CLASSIFIER WITH SENTIMENT ANALYSIS (17656467)

Inventor Takuya Goto

Brief explanation

This abstract describes a method, system, and computer program that involves analyzing a set of documents. The method includes selecting a specific topic and identifying if a document within the set contains a label related to that topic. If it does, a sentiment score is generated for that document and added to a set of training data. If a document does not contain the topic label, an average sentiment score is generated for that document, along with a bias factor.

Abstract

A method, system, and computer program product are disclosed. The method includes receiving a set of documents, selecting a topic, and determining that a first document from the set contains a topic label for the topic. The method also includes generating a topic sentiment score for the first document and adding the topic sentiment score to a set of training data. Additionally, the method includes determining that a second document from the set does not contain the topic label, generating an average sentiment score for the second document, and generating a bias factor for the average sentiment score.

SEARCH BASED ON ABSTRACTED DOCUMENT STRUCTURE IMAGE (17703375)

Inventor SHO AYUBA

Brief explanation

This abstract describes an approach for searching for specific documents. The approach takes a simplified document structure provided by the user and uses it as a reference for the search. It then searches a group of documents based on this structure and creates a pool of potential target documents. The approach displays this pool to the user, who can then choose one or more documents from it.

Abstract

An approach for searching for target documents. The approach receives an abstracted document structure from a user to use as a search source. The approach searches, based on the abstract document structure, a group of search destination documents. The approach creates a pool of target documents based on a portion of the group of search destination documents. The approach displays the pool of target documents to the user, allowing the user to select one or more of the pool of target documents.

AUTOMATIC DETERMINATION AND NOTIFICATION OF IRRITANT RELIEF (17656228)

Inventor Harini Jagannathan

Brief explanation

This abstract describes a system where a processor receives data about irritants in different environments and analyzes it. The processor then identifies irritants that are affecting a user in those environments and generates an alert to notify the user about these irritants. The alert informs the user that at least one irritant is present in the environments they are in.

Abstract

A processor may receive irritant data associated with one or more environments and a user. A processor may analyze the irritant data. A processor may identify that one or more irritants associated with the user, are located in the one or more environments. A processor may generate an irritant alert to the user. The irritant alert may indicate at least one irritant of the one or more irritants is associated with the one or more environments.

DYNAMIC PARKING MANAGEMENT SYSTEM (17654081)

Inventor Yohkichi Sasatani

Brief explanation

The abstract describes a computer system that can identify available parking spaces on a road, assign them to autonomous vehicles, and send the parking space information to the vehicles.

Abstract

Computer hardware and/or software configured to determine a plurality of parking spaces on a roadway within a pre-defined geographic location, wherein the plurality of parking spaces are available parking spaces on a side of the roadway, determine a plurality of autonomous vehicles to be parked within the pre-defined geographic location, allocate a selected parking space from the plurality of parking spaces to an autonomous vehicle of the plurality of autonomous vehicles, and transmit parking space information to the autonomous vehicle, wherein the parking space information includes the selected parking space.

SYNCHRONIZED MEMORY REPAIR SYSTEM (SRS) (17656017)

Inventor Yaron Freiman

Brief explanation

This abstract describes a system, program product, and method for processing synchronized memory repairs. It involves identifying a faulty memory row in a memory array and performing repair operations on it. A repair row is selected to replace the faulty memory row. A multiple hot state is created within a memory decoder, which controls the functioning memory rows. The identified repair row is activated through this multiple hot state, and memory operations are executed on it. This helps to synchronize the repair row with the functioning memory rows in the memory array and any associated peripheral signals.

Abstract

A system, program product, and method for processing synchronized memory repairs. The method includes identifying a faulty memory row from a plurality of functioning memory rows in a memory array. The method also includes executing memory row repair operations directed toward the faulty memory row and identifying a repair row to operationally replace the faulty memory row. The method also includes creating a multiple hot state within a memory decoder. The memory decoder includes logic circuitry for executing operation of the plurality of functioning memory rows. The method further includes activating a wordline of the identified repair row through the multiple hot state, and executing one or more memory operations on the identified repair row though the memory decoder. Accordingly, the embodiments disclosed herein facilitate synchronization of the repair row and functioning memory rows within the memory array, as well as any associated peripheral signals.

COMPUTATION OF A QUALITY OF LIFE METRIC (17656478)

Inventor Pritish Ranjan Parida

Brief explanation

This abstract describes a method, computer system, and computer program that aim to improve the quality of life (QOL) for an individual or a group of individuals. The system receives a dataset containing time-series data related to a specific QOL factor. It then determines the relative importance of this factor for the individual or group and calculates a QOL metric based on this importance. An intervening measure is determined based on the QOL metric. The system can request the application of this measure and modify the QOL metric based on the data derived from the application.

Abstract

A method, computer system, and a computer program for improving a quality of life (QOL) of an individual or a group of individuals is provided. The present invention may include receiving a dataset comprising time-series data pertaining to a QOL factor for the individual or group of individuals. The present invention may then include determining a relative importance of the QOL factor for the individual or group of individuals; computing a QOL metric associated with the individual or group of individuals based on the relative importance of the QOL factor; and determining an intervening measure based on the QOL metric. The present invention may further include requesting an application of the intervening measure based on the QOL metric; and modifying the QOL metric based on a plurality of intervening measure data derived from application of the intervening measure.

STACKED DEVICE WITH BURIED INTERCONNECT (17656174)

Inventor Ruilong XIE

Brief explanation

The abstract describes a layout and fabrication method for stacked field-effect transistors (FETs). These stacked FETs have a buried interconnect that supplies power to buried components without the need for wired connections from the top of the stacked FET to the buried components. This buried interconnect enables efficient scaling of the stacked devices without the need for excessive wiring from the top of the device to each epitaxial region or device within the overall device.

Abstract

A stacked field-effect transistors (FETs) layout and a method for fabrication are provided. The stacked FETs include a buried interconnect within the stacked devices which provides power to buried components without requiring a wired connection from a top of the stacked FET to the buried components. The buried interconnect allows for efficient scaling of the stacked devices without extraneous wiring from a top of the device to each epitaxial region/device within the overall device.

MULTICHIP INTERCONNECT PACKAGE (17942149)

Inventor Akihiro Horibe

Brief explanation

The abstract describes a structure made up of interconnected semiconductor components. It includes an interconnect structure, two semiconductor dies bonded to different parts of the structure, and a resin layer filling the gap between the two dies. The resin layer has a concave meniscus shape on at least one of its surfaces.

Abstract

An interconnected semiconductor subassembly structure includes an interconnect structure; a first semiconductor die bonded to a first portion of a top surface of the interconnect structure; a second semiconductor die bonded to a second portion of the top surface of the interconnect structure; and a resin layer located within at least a first portion of a gap between the first semiconductor die and the second semiconductor die, wherein at least one of a top surface and a bottom surface of the resin layer located within the at least first portion of the gap has a concave meniscus shape.

SEMICONDUCTOR DEVICE DESIGN MITIGATING LATCH-UP (17656368)

Inventor David WOLPERT

Brief explanation

The abstract describes an apparatus designed to prevent latch-up in semiconductor devices. It explains that the device includes three conductors - a first conductor, a second conductor, and a first gate conductor. The first conductor receives a power supply signal and is connected to a first electrode, while the second conductor receives a different power supply signal and is connected to a second electrode. To prevent the formation of parasitic devices that could cause latch-up, the first conductor is positioned offset from the second conductor in a direction perpendicular to their extension. The first gate conductor is located adjacent to the first and second conductors, placed on the first and second electrodes, and receives an input signal.

Abstract

Apparatus for mitigating latch-up within semiconductor devices. A semiconductor device includes a first conductor, a second conductor, and a first gate conductor. The first conductor extends in a first direction, receives a first power supply signal, and is connected to a first electrode. The second conductor extends in the first direction, receives a second power supply signal different from the first power supply signal, and is connected to a second electrode. The first conductor is offset from the second conductor in a second direction perpendicular to the first direction in a top-down view to mitigate formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor. The first gate conductor is disposed adjacent to the first conductor and the second conductor, is disposed on the first electrode and the second electrode, and receives an input signal.

MULTICHIP INTERCONNECT PACKAGE FINE JET UNDERFILL (17704061)

Inventor Akihiro Horibe

Brief explanation

The abstract describes a structure made up of interconnected semiconductor components. It includes an interconnect structure and two semiconductor dies that are bonded to different parts of the structure. The structure also has an underfill layer that fills gaps between the semiconductor dies and the interconnect structure. The underfill layer has a concave shape on the top surface between the two semiconductor dies.

Abstract

An interconnected semicondcutor subassembly structure and formation thereof. The interconnected semicondcutor subassembly structure includes an interconnect structure, and first and second semicondcutor dies bonded to respective portions of a top surface of the interconnect structure. The interconnected semicondcutor subassembly structure further includes an underfill layer formed within a first gap located between a bottom surface of the first semiconductor die and the first portion the top surface of the interconnect structure, formed within a second gap located between the bottom surface of the second semiconductor die and the second portion of the top surface of the interconnect structure, and formed within a first portion of a third gap located between the first semicondcutor die and the second semicondcutor die. A top surface of the underfill layer formed within the first portion of the third gap located between the first and second semicondcutor dies has a concave meniscus shape.

BOTTOM CONTACT WITH SELF-ALIGNED SPACER FOR STACKED SEMICONDUCTOR DEVICES (17655807)

Inventor GEN TSUTSUI

Brief explanation

This abstract describes an approach for creating a semiconductor structure made up of multiple stacked semiconductor devices. The structure includes a top semiconductor device, a bottom semiconductor device below the top one, and contacts to each of the devices. The approach allows for the creation of a stacked structure where the bottom device is wider than the top device. It also allows for a stacked structure where the width of the top device is the same as the width of the bottom device. The approach involves forming a contact to the side of the bottom device when the widths are the same, and forming a contact to epitaxy (a layer of semiconductor material grown on another material) on the top and side of the bottom device when the bottom device is larger than the top device.

Abstract

An approach forming semiconductor structure composed of one or more stacked semiconductor devices that include at least a top semiconductor device, a bottom semiconductor device under the top semiconductor, and contacts to each of the semiconductor devices. The approach provides a stacked semiconductor structure where the bottom semiconductor device is wider than the top semiconductor device. The approach also provides the stacked semiconductor structure where the width of the top semiconductor device is the same as the width of the bottom semiconductor device. The approach includes forming a contact to a side of the bottom semiconductor device when the width of the top semiconductor device is the same as the bottom semiconductor device. The approach includes forming a contact to epitaxy grown on a portion of the top and a side of the bottom semiconductor device when the bottom semiconductor device is larger than the top semiconductor device.

STACKED FETS INCLUDING DEVICES WITH THICK GATE OXIDE (17656553)

Inventor Ruilong Xie

Brief explanation

This abstract describes a semiconductor device that consists of two layers. The first layer contains a standard-gate field-effect transistor, while the second layer contains an extended-gate field-effect transistor. These two layers are stacked on top of each other.

Abstract

A semiconductor device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer of the semiconductor device includes a standard-gate field-effect transistor. The second semiconductor layer of the semiconductor device includes an extended-gate field-effect transistor. The first semiconductor layer and the second semiconductor layer are formed on top of one another.

STAGGERED STACKED CIRCUITS WITH INCREASED EFFECTIVE WIDTH (17701015)

Inventor Brent A Anderson

Brief explanation

This abstract describes a semiconductor structure that consists of two logic cells. The first logic cell contains a group of nanosheet devices arranged along an axis, and the second logic cell also contains nanosheet devices arranged along the same axis. However, the nanosheets in the second logic cell are wider than those in the first logic cell. Both logic cells can be of the same type and can include inverter circuits, NAND circuits, or NOR circuits. The dimensions of the first logic cell are given as height X, width Y, and effective width Z. In comparison, the second logic cell has a height of 2X, the same width Y, and an effective width (W) that is greater than 2.5 times Z.

Abstract

A semiconductor structure including a first logic cell having a first plurality of nanosheet devices along an axis and a second logic cell having a second plurality of nanosheet devices along the axis. Nanosheets of the second plurality of nanosheet devices are wider than nanosheets of the first plurality of nanosheet devices. The first logic cell is a same type as the second logic cell. The first and second logic cells can include inverter circuits or NAND circuits or NOR circuits. When the first logic cell has a height X, a width Y, and an effective width (W) Z, then the second logic cell has a height 2X, a width Y, and W>2.5 Z.

BOTTOM DIELECTRIC ISOLATION FOR VERTICALLY STACKED DEVICES (17655797)

Inventor Sanjay C. Mehta

Brief explanation

The abstract describes a structure and a method for creating a nanosheet stack with a shallow trench isolation region. The structure includes two nanosheet stacks with a shallow trench isolation region between them. A continuous dielectric layer is present below the nanosheet stacks and above the shallow trench isolation region. The shallow trench isolation region is aligned with a source drain between the nanosheet stacks. The method involves forming the nanosheet stacks on a substrate, where each stack consists of alternating layers of sacrificial material and semiconductor channel material. The first substrate is then flipped over and bonded to a second substrate, which includes the shallow trench isolation region.

Abstract

A first and a second nanosheet stack, a shallow trench isolation region vertically aligned between them, a continuous dielectric layer below the first and second nanosheet stack and above the shallow trench isolation region. The shallow trench isolation region is vertically aligned with a source drain between the first and the second nanosheet stack. A method including forming a first and a second nanosheet stack on a first substrate, the first and the second nanosheet stack each including a lower nanosheet stack vertically aligned above an upper nanosheet stack, the upper nanosheet stack and the lower nanosheet stack each including alternating layers of a sacrificial material and a semiconductor channel material vertically aligned and stacked one on top of another, flipping the first substrate over, bonding an upper surface of the first substrate to an upper surface of a second substrate which includes a shallow trench isolation region.

HORIZONTALLY STACKED NANOSHEET GATE ALL AROUND DEVICE STRUCTURE (17701772)

Inventor Shogo Mochizuki

Brief explanation

The abstract describes a semiconductor structure that consists of several components. These components include a substrate, which is a base material, a gate metal placed on the substrate, and two spacers positioned on the substrate with the gate metal in between. Additionally, there are multiple nanosheets that are stacked horizontally between the two spacers. The gate metal surrounds and protects these stacked nanosheets.

Abstract

A semiconductor structure includes a substrate disposed in a horizontal plane, a gate metal on the substrate, a first spacer and a second spacer on the substrate with the gate metal between the first spacer and the second spacer, and a plurality of horizontally stacked nanosheets extending between the first spacer and the second spacer, with the gate metal encapsulating the plurality of horizontally stacked nanosheets between the first spacer and the second spacer.

HIGH-DENSITY EMBEDDED BROADSIDE-COUPLED ATTENUATORS (17656678)

Inventor Nicholas A Masluk

Brief explanation

The abstract describes systems and techniques for creating high-density embedded broadside-coupled attenuators. These attenuators consist of an output line and a reflectively-terminated input line that is broadside coupled to the output line. The downstream end of the reflectively-terminated input line can either be shorted to ground or open from ground. The output line is designed in a non-looped-back layout.

Abstract

Systems and techniques that facilitate high-density embedded broadside-coupled attenuators are provided. In various embodiments, an attenuator can comprise an output line. In various aspects, the attenuator can further comprise a reflectively-terminated input line that is broadside coupled to the output line. In various instances, a downstream end of the reflectively-terminated input line can be shorted to ground. In other instances, a downstream end of the reflectively-terminated input line can be open from ground. In various cases, the output line can exhibit a non-looped-back-layout.

ELECTROPLATED METAL LAYER ON A NIOBIUM-TITANIUM SUBSTRATE (18316060)

Inventor Ryan T. Gordon

Brief explanation

This abstract describes devices, systems, and methods for plating metal layers onto a niobium-titanium substrate. The device mentioned in the abstract consists of a niobium-titanium substrate, with a first metal layer plated on a portion of it. On top of the first metal layer, there is a second metal layer, and on top of that, a third metal layer.

Abstract

Devices, systems, and/or methods that can facilitate plating one or more metal layers onto a niobium-titanium substrate are provided. According to an embodiment, a device can comprise a niobium-titanium substrate. The device can further comprise a first metal layer plated on a portion of the niobium-titanium substrate. The device can further comprise a second metal layer plated on the first metal layer. The device can further comprise a third metal layer plated on the second metal layer.

BACKUP POWER ALLOCATION MANAGEMENT (17656239)

Inventor Marc Henri Coq

Brief explanation

This abstract describes a method that involves obtaining data about electronic devices, such as their power usage, as well as information about a backup power source's capacity. The method also includes obtaining priority data for allocating power to the devices and environmental conditions. Using this data, the method calculates the projected electrical load on the backup power source and determines if any thresholds are exceeded, particularly if the projected load exceeds the capacity. If thresholds are exceeded, the method modifies the power supplied to the electronic devices based on the priority data.

Abstract

A method can include obtaining device data for a set of electronic devices. The device data can indicate power utilized by the set of electronic devices. The method can include obtaining a capacity of a backup power source. The method can include obtaining priority data regarding an allocation of power to the set of electronic devices. The method can include obtaining a set of environmental conditions. The method can include calculating, based at least in part on the set of environmental conditions and the device data, a projected electrical load on the backup power source. The method can include determining that one or more thresholds are exceeded. The determining can comprise identifying that the projected electrical load exceeds the capacity. The method can include modifying, in response to the determining and according to the priority data, power supplied to the set of electronic devices from the backup power source.

REDUCED LOGIC CONVERSION OF BINARY INTEGERS TO BINARY CODED DECIMALS (17704674)

Inventor KERSTIN CLAUDIA SCHELM

Brief explanation

The abstract describes a method for converting binary numbers into binary coded decimals using reduced logic. The process involves generating an intermediate value with all zero digits in a specific format. Then, each bit of the binary number is shifted into the intermediate value. The intermediate value is then doubled and converted into a binary coded decimal output. The intermediate format includes bits that represent different weights for each digit, with the first bit representing a weight of one and the second bit representing the inverse of that weight.

Abstract

Reduced logic conversion of binary integers to binary coded decimals, including: generating, from an input binary integer, an intermediate value comprising all zero digits encoded in an intermediate format; until each bit of the input binary integer has been shifted into the intermediate value: shifting a bit of the input binary integer into the intermediate value; doubling the intermediate value; converting the intermediate value to a binary encoded decimal output; and wherein the intermediate format comprises, for each digit of the intermediate value, a plurality of bits corresponding to a plurality of even weights, a first bit corresponding to a one weight, and a second bit corresponding to an inverse of the one weight.

PAIRING DEVICES FOR ENHANCED SECURITY (17656685)

Inventor Eric J. Campbell

Brief explanation

This abstract describes a system and method for securely connecting a removable component to a host device, such as a server rack. The host device stores a first pairing key in a security module. When the removable component is inserted into the server rack for the first time, the first pairing key is burned into the component using physically modifiable internal components. The removable component then sends a request to the security module, including the burned-in pairing key. The security module compares the received pairing key with the first pairing key and allows the removable component to operate if there is a match.

Abstract

A system and method to tie a removable component to a host device. A first pairing key is stored into a security module on a host device such as a server rack. A removable component is inserted into the server rack for the first time. In response to this first insertion the first pairing key is burned into the removable component using a plurality of physically modifiable internal components. The server rack/security module receives a request form the removable component to operate on the server rack, the request includes a burned in pairing key. The security module compares the received pairing key with the first pairing key and permits operation of the removable component in response to a match between the received pairing key and the first pairing key.

SESSION RESUMPTION WITH DERIVED KEY (17656787)

Inventor Mark Duane Seaborn

Brief explanation

This abstract describes a method for resuming cryptographic communications between a client and a server. When a client sends session data and encrypted early data to the server, the server derives a key using the session data and a one-time pad. This key is then used to decrypt the early data, allowing the server to resume the communication session with the client.

Abstract

Session resumption for cryptographic communications is provided. Session data and encrypted early data are received from a client. A key is derived using the session data and a one-time pad. The early data is decrypted using the derived key.

CREATING NON-FUNGIBLE TOKEN SHARDS (17655872)

Inventor Luis Angel Bathen

Brief explanation

The abstract describes a process in a blockchain network where a node can divide a non-fungible token (NFT) into smaller parts called geometric shards. Each shard is associated with a specific portion of the NFT. This fractionalization process is recorded on a distributed ledger of the blockchain network.

Abstract

A node in a blockchain network may send an operation for geometrically fractionalizing an non-fungible token (NFT) into geometric shards to a blockchain network. The geometric fractionalization associates each geometric shard with a specific part of the NFT. The node may also record, on distributed ledger of the blockchain network, the fractionalization of the NFT and the association between each geometric shard with the specific part of the NFT.

DATA MIGRATION IN APPLICATION PERFORMANCE MONITORING (17654287)

Inventor Laurentiu Gabriel Ghergu

Brief explanation

This abstract describes a method to enhance data migration in application performance monitoring. The method involves performing a synthetic transaction, which is a simulated interaction with an application, and monitoring the network traffic during this transaction. Various parameters related to the synthetic transaction are extracted from the network traffic. Using these parameters and a predefined template, a script is generated to recreate the synthetic transaction.

Abstract

In an approach to improve data migration in application performance monitoring, embodiments execute a synthetic transaction to monitor an application, and monitor network traffic during the execution of the synthetic transaction. Further, embodiments extract a plurality of parameters indicative of the synthetic transaction from the network traffic, and generate a script, based on the extracted plurality of parameters and a predetermined template, that generates the synthetic transaction.

AUTHENTICATING AND AUTHORIZING API CALLS WITH MULTIPLE FACTORS (17701861)

Inventor Martin Smolny

Brief explanation

This abstract describes a method for verifying and granting access to a service for a user. The service requires two-factor authentication, meaning the user needs to provide two pieces of information to prove their identity. The method involves receiving a service request along with two sets of data for two different authentication methods. The first set of data is used to confirm the user's identity using the first authentication method. The second set of data is then used to confirm the user's identity using a different authentication method, and the first set of data is also input into this second method. Once both sets of data are confirmed to be correct, the service is executed and the user is granted access.

Abstract

A method for authenticating and authorizing a user identifier to access a service is disclosed. The service is activated by a service application programming interface which requires a two-factor authorization to initiate execution of the service for the requesting user identifier. The method receives, by the service API, a service request together with first and second data for a first and a second authentication method, confirming a correctness of the first data as a first identity pass key using the first authentication method, confirming a correctness of the second data as a second identity pass key using the second authentication method and the first identity pass key is input to the second authentication method, and the second authentication method differs from the first authentication method. Having received the confirmed correctness of both the first identity pass key and the second identity pass key, executing the service.

BEHAVIOR DRIVEN SECURITY FOR IOT DEVICES (17656327)

Inventor Pierpaolo Tommasi

Brief explanation

This abstract describes a method, system, and computer program for enhancing the security of Internet of Things (IoT) devices based on their behavior. The method involves detecting actions performed by a set of IoT devices and identifying the context in which these actions occur. The actions and context are then validated for each IoT device. If an action is found to be abnormal based on this validation, a potential state change for the device is identified. Finally, a responsive action is determined based on the potential state change and the anomaly detected.

Abstract

A method, system, and computer program product for behavior-based Internet of Things (IoT) device security are provided. The method detects an action from a set of IoT devices. A context is identified for the action and at least one IoT device of the set of IoT devices. The action and the context are validated for the at least one IoT device. The action is identified as an anomaly based on the validating of the action and the context. A potential state change is identified for the at least one IoT device based on the anomaly. The method determines a responsive action based on the potential state change and the anomaly.

SOUND-BASED PRESENTATION ATTACK DETECTION (17656658)

Inventor Mark S. Fredrickson

Brief explanation

The abstract describes techniques for detecting presentation attacks during a video conference. The method involves emitting a specific frequency pattern through a speaker connected to a computer. Simultaneously, a camera connected to the computer captures video data of the user participating in the video conference. The method then analyzes the video data to determine if it matches the expected response to the emitted frequency pattern. If the video data is inconsistent, it indicates that the user is likely performing a presentation attack, and an indication is generated to alert the video conference participants.

Abstract

Described are techniques for presentation attack detection including a computer-implemented method of emitting a predetermined frequency pattern using at least one speaker communicatively coupled to a computer implementing a video-conference. The computer-implemented method further comprises collecting, by a camera communicatively coupled to the computer and overlapping with the emitting the predetermined frequency pattern, video data of a user engaged in the video-conference. The computer-implemented method further comprises determining that the video data is inconsistent with an expected response to the predetermined frequency pattern. The computer-implemented method further comprises generating an indication that the user engaged in the video-conference is performing a presentation attack.

WORKFLOW PENETRATION TESTING (17656005)

Inventor Daniel Alan Pagan

Brief explanation

This abstract describes a method for conducting penetration testing using multiple tools. The method involves receiving a workflow that contains instructions for executing different penetration testing tools. The workflow is then provided to a workflow runtime manager, which generates worker containers for each tool. These containers execute the tools using specific runtimes. The first tool is executed using the first runtime, and the second tool is executed using the second runtime. The method allows for the efficient execution of multiple penetration testing tools in a coordinated manner.

Abstract

Embodiments are disclosed for a method. The method includes receiving a submitted workflow for penetration testing. The submitted workflow includes execution instructions for a multiple penetration testing tools. The method also includes providing the submitted workflow for a workflow runtime manager. Additionally, the method includes generating, by the workflow runtime manager, a first worker container that executes a first penetration testing tool of the penetration testing tools, using a first runtime. The method further includes executing the first penetration testing tool. Also, the method includes generating, by the workflow runtime manager, a second worker container that executes a second penetration testing tool of the penetration testing tools, using a second runtime. Further, the method includes executing the second penetration testing tool.

SMART SDN FOR INTRUSION PREVENTION (17655821)

Inventor Jeff Hsueh-Chang Kuo

Brief explanation

This abstract describes a method, computer system, and computer program product for smart Software-Defined Networking (SDN). The invention involves recording and grouping the actions of a network device (referred to as a "pod") to create a model of its behavior. The system then monitors the pod's behavior and compares it to the behavior model. If the pod's behavior deviates from the expected model, the system triggers a change in the network's policies to address the misbehavior.

Abstract

A method, computer system, and a computer program product for smart SDN is provided. The present invention may include recording and clustering a pod's behavior to generate a behavior transition model for the pod. The present invention may include watching a behavior of the pod and comparing the behavior to the generated behavior transition model. The present invention may include triggering a network policy change based on determining that the behavior of the pod is a misbehavior.

LINE-DRAWING VIDEO CONFERENCING (17656102)

Inventor Ilse M. Breedvelt-Schouten

Brief explanation

This abstract describes a method, computer system, and computer program product for optimizing web conferencing. The system receives data for an organization with multiple participants and a scheduled web conference. It determines a network bandwidth threshold for each participant based on the organization's data and the scheduled conference's data. The system then monitors the network bandwidth during the conference and decides whether to transmit a line art drawing to participants based on their network bandwidth.

Abstract

A method, computer system, and a computer program product for optimizing web conferencing is provided. The present invention may include receiving data for an organization, the organization being comprised of a plurality of participants. The present invention may include receiving a scheduled web conference. The present invention may include determining a network bandwidth threshold for each of the plurality of participants of the scheduled web conference based on at least the data received for the organization and data associated with the scheduled web conference. The present invention may include monitoring a network bandwidth of the scheduled web conference. The present invention may include determining whether to transmit a line art drawing for one or more participants based on the network bandwidth of the scheduled web conference.

DIGITAL TWIN SIMULATION OF INTERACTIVE VOICE RESPONSE SYSTEM CALL (17655997)

Inventor Partho Ghosh

Brief explanation

This abstract describes a system that simulates an interactive voice response system (IVRS) call using a digital twin agent of a user. The system receives data about the user's characteristics, activities, and past IVRS dialogs. It then creates a digital twin agent of the user and identifies the user's preferences from the historical data. If the user is occupied, the system determines the context of the issue that requires an IVRS call. It then initiates the IVRS call with the digital twin agent and interacts with the IVRS based on the script and the user's preferences.

Abstract

An embodiment for simulating an interactive voice response system (IVRS) call with a digital twin agent of a user is provided. The embodiment may include receiving data relating to characteristics of the user, activities of the user, and historical data relating to one or more prior IVRS dialogs. The embodiment may also include creating a digital twin agent of the user. The embodiment may further include identifying one or more preferences of the user from the historical data. The embodiment may also include in response to determining the user is occupied, identifying a context of an issue requiring an IVRS call. The embodiment may further include initiating the IVRS call with the digital twin agent representing the user. The embodiment may also include transcribing an IVRS script and interacting with the IVRS in accordance with the IVRS script and the one or more preferences of the user.

PROVIDING CONTROLLED ACCESS TO CONTENT ON A CLIENT SYSTEM (17656259)

Inventor Alexander Esam

Brief explanation

This abstract describes a method for controlling access to content on a client system. The system works by embedding a token, which acts as a key, within a media file on the client system. The protected content can only be accessed when certain conditions specified by the media file are met. Once these conditions are satisfied, the token is released to the client system, allowing access to the protected content.

Abstract

Providing controlled access to content on a client system by providing protected content on a client system where the content is accessible with a token and providing a media file at the client system with the token embedded in association with the media file. The protected content is accessed by releasing the token to the client system when it is determined that an action condition of the media file has been met and using the token to enable access to the protected content on the client system.

MULTIPLE ENTITY VIDEO CAPTURE COORDINATION (17704719)

Inventor Jana H. Jenkins

Brief explanation

The abstract describes a process where a video stream of a subject in an environment is captured from a first perspective using a first capture device. When a request is made to change the perspective of the video stream, one or more other capture devices in the environment are detected. A second capture device is selected and instructed to perform the capture operation from the new perspective. The video stream is then transferred from the first capture device to the second capture device, updating the perspective of the video stream.

Abstract

A capture operation is identified. The capture operation is of a video stream of a subject located in an environment. The capture operation is performed by a first capture device from a first perspective of the subject. A perspective update request of the video stream is received. In response to the perspective update request, one or more candidate capture devices in the environment is detected. A second capture device is selected as a selected capture device, from the one or more candidate capture devices. The second capture device is instructing to perform the capture operation based on the selection. The video stream is transferred from the first capture device to the second capture device. The transferring updates the video stream to a second perspective of the subject.

MULTIPLE ENTITY VIDEO CAPTURE COORDINATION (17704471)

Inventor Jana H. Jenkins

Brief explanation

The abstract describes a system where a first capture device is used to capture a video stream of a subject in an environment. However, if the first capture device has limitations in capturing the subject, one or more other candidate capture devices in the environment are detected. From these candidates, a second capture device is selected and instructed to perform the capture operation instead. The video stream is then transferred from the first capture device to the second capture device while maintaining the same perspective.

Abstract

A capture operation is identified. The capture operation is performed by a first capture device. The capture operation is of a video steam of a subject that is located in an environment. The video stream includes a perspective of the subject. A capture limitation of the first capture device, related to capturing the subject, is determined. In response to the capture limitation one or more candidate capture devices in the environment are detected. A second capture device is selected as a selected capture device, from the one or more candidate capture devices. The second capture device is instructed to perform the capture operation. The video stream is transferred from the first capture device to the second capture device; the transfer maintains the perspective.

DYNAMIC MANAGEMENT OF A SOUND FIELD (17656230)

Inventor Shailendra Moyal

Brief explanation

This abstract describes a processor that can analyze sound data from a specific environment to identify external and internal sound sources. It can then generate simulations of the sound field based on user preferences and modify the sound field within that environment accordingly.

Abstract

A processor may receive sound data associated with a bounded environment. The sound data may be associated the sound data is associated with a sound field. The processor may analyze the sound data associated with the sound field to identify one or more external sound sources and one or more internal sound sources. The processor may generate one or more simulations of the sound field based, at least in part, on a user preference set. The processor may modify a sound field within the bounded environment. The modified sound field may be based, at least in part, on the one or more simulations of the sound field and the user preference set.

RESOURCE MANAGEMENT AND LOGICAL CHANNEL AGGREGATION FOR 5G NETWORKS (17656655)

Inventor Grzegorz Piotr Szczepanik

Brief explanation

The abstract describes a method for balancing the workload of processors in an eNodeB (a component of a wireless communication network). When a processor core is not being fully utilized, the method identifies this and transfers the communication traffic to another core. The underutilized core then goes into sleep mode until it is needed again. This helps optimize the use of resources in the network.

Abstract

Resource load balancing for eNodeB includes identifying reduced workload conditions for an underutilized processor (CPU) core and transferring dedicated traffic channel (DTCH) communication to a target CPU core. Upon migrating each DTCH from the selected CPU core, the underutilized CPU core is caused to go into sleep mode, not to receive DTCH request until activated.

REGISTERED EDGE DEVICE MANAGEMENT (17655842)

Inventor Akira Saito

Brief explanation

This abstract describes a method that involves collecting data from a group of edge devices and predicting the travel path of a specific entity. The method then determines the proximity of one of the edge devices to the predicted travel path and selects it based on this proximity. A workload is then sent to the selected edge device, and the first captured data obtained by the device is received and transmitted to an electronic user device.

Abstract

A method can include obtaining device data for a set of edge devices. The method can further include obtaining a predicted travel path of a focal entity. The method can further include determining, for a first edge device of the set of edge devices and based on the device data, a first proximity of the first edge device to the predicted travel path. The method can further include selecting the first edge device based, at least in part, on the first proximity. The method can further include transmitting, in response to the selecting the first edge device, a workload to the first edge device. The method can further include receiving, in response to the transmitting the workload, first captured data obtained by the first edge device. The method can further include transmitting the first captured data to an electronic user device.

EMBEDDED MAGNETORESISTIVE RANDOM ACCESS MEMORY (17656045)

Inventor Heng Wu

Brief explanation

The abstract describes a system that includes a semiconductor structure. This structure consists of a wafer, multiple transistors, and a magnetoresistive random access memory (MRAM) cell. The transistors are located on the front end of the wafer, while the MRAM cell is placed on the backside of the wafer. The MRAM cell is connected to the transistors through a contact on the backside of the wafer. The transistors and the MRAM cell are directly connected through at least one contact.

Abstract

Embodiments are disclosed for a system. The system includes a semiconductor structure. The semiconductor structure includes a wafer, multiple transistors, and a magnetoresistive random access memory (MRAM) cell disposed on the backside of the wafer. The transistors are disposed on a front end of line (FEOL) of the wafer. The MRAM cell is connected to a source-drain of the transistors by a contact disposed on the backside of the wafer. The transistors are in direct electrical contact with the MRAM cell by at least one contact.

HIGH DENSITY MEMORY WITH STACKED NANOSHEET TRANSISTORS (17705320)

Inventor Heng Wu

Brief explanation

The abstract describes a high density memory apparatus that consists of multiple transistors stacked vertically on top of each other. These transistors share a common source structure but have their own separate horizontal nanosheet and gate stack. The ends of the nanosheets, which are far from the gate stacks, are doped to act as drains for the transistors. Each nanosheet is connected to a two-terminal memory unit. Some embodiments of this memory apparatus can achieve more than 5000 memory bits per square micrometer, and in some cases, more than 6000 bits per micrometer.

Abstract

A high density memory apparatus includes a plurality of transistors vertically stacked on top of each other. The plurality of transistors share a common source structure, but each of the plurality of transistors has its own horizontal nanosheet and gate stack that are separate from respective horizontal channel structures and gate stacks of the others of the plurality of transistors. Ends of the nanosheets distal from the gate stacks are doped to act as drains for the transistors. Each of a plurality of two-terminal memory units is electrically connected to the drain end of a corresponding one of the nanosheets. Some embodiments achieve in excess of 5000 memory bits/square micrometer (μm); in some embodiments, in excess of 6000 bits/μm.

TEMPERATURE INDICATOR POWERED BY THERMOELECTRIC GENERATOR (17656664)

Inventor Noah Singer

Brief explanation

The abstract describes a system for electronic heatsink safety. The system includes a thermoelectric generator integrated into a heatsink. The thermoelectric generator has two parts - one exposed to ambient temperature and the other in contact with the heatsink. The generator produces a current based on the temperature difference between these two parts. The system also includes a LED that is connected to the thermoelectric generator and is activated by the current produced.

Abstract

Described are systems for electronic heatsink safety including a system comprising a thermoelectric generator integrated into a heatsink, where the thermoelectric generator includes a first portion exposed to ambient temperature and a second portion contacting the heatsink, and where the thermoelectric generator is configured to produce a current based on a temperature difference between the first portion and the second portion. The system further comprises a first Light Emitting Diode (LED) electrically connected to the thermoelectric generator, where the current is configured to activate the first LED.

ADVANCED MRAM DEVICE STRUCTURE (17655795)

Inventor Oscar van der Straten

Brief explanation

The abstract describes a type of MRAM (Magnetoresistive Random Access Memory) cell that consists of different layers. The lower section includes a bottom electrode, a synthetic anti-ferromagnet layer, and a reference layer. These layers have angled sidewalls. There is a dielectric cap on top of the lower section. The upper section includes a tunnel barrier, a free layer, and a top electrode. The tunnel barrier has angled side sections located on top of a second dielectric liner made of a different material.

Abstract

A MRAM Cell including a dielectric cap and a lower section that includes a bottom electrode, a synthetic anti-ferromagnet layer, and a reference layer, where in the sidewalls of each of the bottom electrode, the synthetic anti-ferromagnet layer, and the reference layer are angled relative to the vertical plane perpendicular to a top surface of the dielectric cap. A first dielectric liner located on the sidewalls of each of the lower section. An upper section that includes a tunnel barrier, a free layer, and a top electrode. A second dielectric liner located on a side section of the tunnel barrier, where the second dielectric liner is comprised of a second material, and where the angled side sections of the tunnel barrier are located on top of the second dielectric liner.

ANTENNA ASSISTED RERAM FORMATION (18205208)

Inventor Youngseok Kim

Brief explanation

This abstract describes a memory structure that uses a ReRAM module embedded in a substrate. The structure includes an insulative layer, a first electrode connected to one end of the ReRAM module, and a second electrode connected to the other end of the ReRAM module. The second electrode has a plasma-interacting component, a resistive component, and a different surface area compared to the first electrode. When exposed to plasma, the voltage created between the two electrodes forms a conductive filament in the ReRAM module.

Abstract

A memory structure comprises a ReRAM module embedded in a substrate. An insulative layer is formed on the substrate. A first electrode is located on the insulative layer. The first electrode is proximately connected to a first end of the ReRAM module and comprises a first surface area. A second electrode is located on the insulative layer. The second electrode is proximately connected to a second end of the ReRAM module. The second electrode comprises a second surface area, a plasma-interacting component, and a resistive component. The resistive component is located between the plasma-interacting component and the ReRAM module. A ratio of the first surface area to the second surface area creates a voltage between the first electrode and second electrode when the first surface area and second surfaces area are exposed to an application of plasma. The voltage forms a conductive filament in the ReRAM module.

PHASE CHANGE MEMORY CELL WITH OVONIC THRESHOLD SWITCH (18311922)

Inventor Nanbo Gong

Brief explanation

The abstract describes a structure and method for creating a device that includes a bottom electrode, a layer of phase change material, and an ovonic threshold switching layer. The layers are vertically aligned, with a first barrier layer separating the ovonic threshold switching layer from a top electrode. The method involves forming the layers in a specific order and surrounding them with a dielectric material. The vertical side surfaces of the layers are also aligned with each other.

Abstract

A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.

LATERAL PHASE CHANGE MEMORY CELL (17656430)

Inventor Timothy Mathew Philip

Brief explanation

The abstract describes a structure and method for creating a device with an inner electrode, an outer electrode, and a layer of phase change material. The phase change material layer is positioned vertically above both electrodes on a substrate. The method involves simultaneously forming the inner and outer electrodes on the substrate and then adding the phase change material layer above them.

Abstract

A structure including an inner electrode and an outer electrode on a substrate and a phase change material layer, the phase change material layer vertically aligned above both the inner electrode and the outer electrode. A structure including an inner electrode and an outer electrode on a substrate and a phase change material layer, the phase change material layer vertically aligned above both the inner electrode and the outer electrode, where the inner electrode and the outer electrode are on the same horizontal plane. A method including forming an inner electrode and an outer electrode simultaneously on a substrate, forming a phase change material layer above both the inner electrode and the outer electrode.