International Business Machines Corporation patent applications on March 21st, 2024
Patent Applications by International Business Machines Corporation on March 21st, 2024
International Business Machines Corporation: 99 patent applications
International Business Machines Corporation has applied for patents in the areas of H01L29/775 (18), H01L29/06 (13), H01L29/0673 (12), H01L23/528 (10), H01L29/66 (10)
With keywords such as: structure, based, device, data, user, layer, computer, dielectric, embodiment, and source in patent application abstracts.
Patent Applications by International Business Machines Corporation
Inventor(s): Sneha Kanaujia of Lexington MA (US) for international business machines corporation, Al Chakra of Apex NC (US) for international business machines corporation, Bryan Childs of Poughkeepsie NY (US) for international business machines corporation, GREGORY C. CREMINS of Poughkeepsie NY (US) for international business machines corporation, Travis Biro of Cold Spring NY (US) for international business machines corporation, Andrew C. M. Hicks of Highland NY (US) for international business machines corporation, Cecilia Carranza Lewis of San Jose CA (US) for international business machines corporation, Peter G. Spera of Pleasant Valley NY (US) for international business machines corporation
IPC Code(s): A63F13/798, A63F13/46, H04L9/00
Abstract: an anonymous leaderboard for a monitored computing environments is provided. in response to an entity registering with the monitored computing environment (mce), an encrypted identity and a dynamic non-fungible token (nft) are generated for the registered entity, where the dynamic nft has an associated blockchain technology data structure. the blockchain technology data structure is associated with the encrypted identity. a progress element notification is received from the mce in response to the entity satisfying criteria for a predefined progress element associated with the mce. in response, a static nft, corresponding to the predefined progress element, is generated and stored as a block in the blockchain technology data structure. an entry in an anonymous leaderboard output is generated based on the blockchain technology data structure, where the entry identifies the entity by the encrypted identity.
Inventor(s): Roberto Ragusa of Rome (IT) for international business machines corporation, Remo Freddi of Ronciglione (IT) for international business machines corporation, Chiara Conti of Rome (IT) for international business machines corporation, Alessandra Asaro of Rome (IT) for international business machines corporation
IPC Code(s): B60W30/09, B60W30/095, G06V20/58
Abstract: a method, computer system, and a computer program product for brake detection is provided. the present invention may include determining a first geometric ratio associated with a rear portion of a first vehicle, from a first image of the first vehicle. the present invention may also include determining a second geometric ratio associated with the rear portion of the first vehicle, from a second image of the first vehicle. the present invention may further include, in response to determining that the second geometric ratio is less than the first geometric ratio, detecting a braking action of the first vehicle.
Inventor(s): Tushar Agrawal of West Fargo ND (US) for international business machines corporation, Martin G. Keen of Cary NC (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): B60W40/09
Abstract: a computer-implemented method, in accordance with one embodiment, includes monitoring contextual information of a vehicle during operation thereof. a determination is made that a condition is met to project, by a vehicle-based projection system mounted to the vehicle, a projection indicative of a contextual condition associated with the vehicle. in response to the determination that the condition is met, the projection indicative of the contextual condition is projected.
Inventor(s): Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Shailendra Moyal of Pune (IN) for international business machines corporation
IPC Code(s): G01C21/34, G06Q50/30
Abstract: a method for utilizing augmented reality for positioning vehicles is disclosed. in one embodiment, such a method enables a customer to visualize, by way of an augmented reality device, a desired position of a vehicle selected to arrive at a designated pickup spot. this may include visualizing, by way of the augmented reality device, the desired position within an environment surrounding the pickup spot. the desired position may include one or more of a location and orientation of the vehicle and may be selected to optimize loading of passengers and/or cargo into the vehicle. the method documents the desired position and communicates the desired position to a ride-hailing service to enable the vehicle to be placed in accordance with the desired position upon arriving at the designated pickup spot. a corresponding system and computer program product are also disclosed.
Inventor(s): Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Alexander Reznicek of Troy NY (US) for international business machines corporation, Bahman Hekmatshoartabari of White Plains NY (US) for international business machines corporation, Martin G. Keen of Cary NC (US) for international business machines corporation
IPC Code(s): G06F3/01, G16H40/63
Abstract: according to one embodiment, a method, computer system, and computer program product for biometric mixed-reality emotional modification is provided. the present invention may include collecting, by a plurality of biosensors, biometric information on a user during a mixed-reality session, wherein the biometric information comprises biomarkers; identifying, by one or more machine learning models, a mental state of the user based on the biometric information; and responsive to determining that the mental state does not match an intended emotion associated with a mixed-reality experience, modifying the mixed-reality experience with one or more virtual content elements.
Inventor(s): Xiang Wei Li of Beijing (CN) for international business machines corporation, Dong Chen of Beijing (CN) for international business machines corporation, Ye Chuan Wang of Beijing (CN) for international business machines corporation, Ting Ting Zhan of Beijing (CN) for international business machines corporation, Ju Ling Liu of Beijing (CN) for international business machines corporation, Yu An of Beijing (CN) for international business machines corporation, Wei Yan of Beijing (CN) for international business machines corporation
IPC Code(s): G06F3/04895, G10L15/22
Abstract: a method for selecting an application and associated operational guidance to utilize on a mobile device is disclosed. in one embodiment, such a method identifies a selected environment of interest. within the selected environment, the method identifies one or more applications that are commonly utilized by users within the selected environment and documents the one or more applications. the method detects physical entry of a particular user into the selected environment and, in response to detecting the entry, automatically notifies the particular user of the one or more applications that are commonly utilized within the selected environment. in certain embodiments, the method enables the user to quickly launch the one or more applications and/or provides operational guidance to the user with regard to using the one or more applications. a corresponding system and computer program product are also disclosed.
Inventor(s): Atsushi Abe of Ebina (JP) for international business machines corporation, Tohru Hasegawa of Tokyo (JP) for international business machines corporation, Shinsuke Mitsuma of Machida-shi (JP) for international business machines corporation, Hiroshi Itagaki of Yokohama-shi (JP) for international business machines corporation, Noriko Yamamoto of Tokyo (JP) for international business machines corporation, Tsuyoshi Miyamura of Yokohama-shi (JP) for international business machines corporation, Lucas Correia Villa Real of Sao Paulo (BR) for international business machines corporation
IPC Code(s): G06F3/06
Abstract: a computer implemented method includes receiving a list of areas on a subject tape to be read, wherein each area of the list of areas is indicated by a first record number and a last record number corresponding to the area, identifying parameters of a tape drive configured to read the subject tape, wherein the identified parameters of the tape drive contribute to a speed with which the tape drive can read the list of areas, creating a directed graph of the areas on the subject tape based on the identified parameters, wherein the directed graph indicates how long the tape drive will take to read the areas on the subject tape, and determining a fastest reading order of the areas on the subject tape, based, at least in part, on the directed graph and the identified parameters. a computer program product and computer system are also disclosed.
Inventor(s): Swagatam Haldar of Kolkata (IN) for international business machines corporation, Devika Sondhi of New Delhi (IN) for international business machines corporation, Diptikalyan Saha of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F8/35, G06F9/54
Abstract: a method of providing a surrogate program for a program endpoint includes: obtaining, by a processor set, a set of plural input/output pairs generated using the program endpoint; generating, by the processor set, transformations based on the input/output pairs; generating, by the processor set, a model that classifies inputs of the input/output pairs to ones of the transformations based on parameters of one or more strings of the inputs; receiving, by the processor set, a new input; selecting, by the processor set and using the model, one of the transformations based on parameters of one or more strings of the new input; and generating, by the processor set, a new output by applying the selected one of the transformations to the new input.
Inventor(s): Mark Kunitomi of San Francisco CA (US) for international business machines corporation, David Chambliss of Morgan Hill CA (US) for international business machines corporation, Forest Dussault of Ottawa (CA) for international business machines corporation
IPC Code(s): G06F8/41, G06F8/36, G06F9/455
Abstract: information received from a graphical user interface (gui) and a list of user-curated command line patterns are received by an auto-wrapper system, wherein the auto-wrapper system is associated with an analytics workflow service. a module including a parameter space having one or more parameters and options used in the list of user-curated command line patterns is generated, by the auto-wrapper system, wherein content for each parameter is derived from the parameter's presence in the list of user-curated command line patterns combined with the information received from a gui.
Inventor(s): Kazuaki Ishizaki of Kotoh (JP) for international business machines corporation
IPC Code(s): G06F8/41, G06F9/38
Abstract: a computer-implemented method, system and computer program product for improving the performance of a program that manipulates two vectors of data. it is determined whether the program contains one of the following patterns: a first pattern corresponding to v0.rearrange(s, v1); a second pattern corresponding to v0.blend(v1, m); and a third pattern corresponding to v0.rearrange(s).blend(v1.rearrange(s), m). upon identifying code written as the first pattern in the program, the first pattern is rewritten and replaced with the second or third pattern if the execution time of the program with the second or third pattern is less than the execution time of the program with the first program. in a similar manner, upon identifying code written as the second or third pattern in the program, the second or third pattern is rewritten and replaced with the first pattern if the execution time of the program can be improved.
Inventor(s): Dhavalkumar C. Patel of White Plains NY (US) for international business machines corporation
IPC Code(s): G06F8/61, G06F8/35, G06N20/00
Abstract: using exported data of a machine learning model and a model training environment specification, a resource usage specification and a code module usage specification of the model are identified. a code module installation specification is determined from a code module requirements specification and a target execution environment specification. the code modules specified by the code module installation specification are caused to be installed in the target execution environment. using data of the updated target execution environment, the updated target execution environment is validated for execution of the model. execution of the model in the updated target execution environment is simulated. the model is deployed in the updated target execution environment responsive to the simulating being successful.
Inventor(s): Yue Wang of Beijing (CN) for international business machines corporation, Wei Wu of Beijing (CN) for international business machines corporation, Xin Peng Liu of Beijing (CN) for international business machines corporation, Liang Wang of Beijing (CN) for international business machines corporation, Biao Chai of Beijing (CN) for international business machines corporation
IPC Code(s): G06F9/50, G06F11/07
Abstract: a method includes, in response to receiving an incoming service request and establishing a call chain of pods of a service mesh network, setting a retry locker parameter to a locked state for each pod in the call chain. a locked retry locker parameter prevents the pod from initiating retries of a service request. the method includes, in response to determining that a pod in the call chain is unavailable, setting the retry locker parameter to an unlocked state for a previous pod just prior to the pod that is unavailable. the unlocked state allows a retry to the pod that is unavailable. in response to the previous pod reaching a retry limit, the method includes setting the retry locker parameter to unlocked for each pod in the call chain and sending a service termination message to a service requester.
Inventor(s): Hirokuni Kitahara of Sumida-ku (JP) for international business machines corporation, Yuji Watanabe of Chuouku (JP) for international business machines corporation, Kugamoorthy Gajananan of Toshima-ku (JP) for international business machines corporation, Ruriko Kudo of Saitama-shi (JP) for international business machines corporation
IPC Code(s): G06F9/50, G06F21/55
Abstract: a computer-implemented method for determining container information associated with detected container mutation events is disclosed. the computer-implemented method includes: determining that a system call event to a host operating system includes a call to join a namespace and execute a parent process inside the namespace; determining that the namespace is associated with an existing container; responsive to determining that the namespace is associated with an existing container, determining that the system call event further includes a call to execute a child process inside the namespace; and responsive to determining that the system call event further includes a call to execute a child process inside the namespace: designating the child process as a mutation event to the existing container, and determining container information associated with the mutation event to the existing container. a corresponding computer system and computer program product are also disclosed.
Inventor(s): Hong Liang Zhao of Beijing (CN) for international business machines corporation, Qi Li of Beijing (CN) for international business machines corporation, Yan Hui Wang of Beijing (CN) for international business machines corporation, Jia Lei Rui of Li Yang (CN) for international business machines corporation, Qun Wei of Beijing (CN) for international business machines corporation, Yun Juan Yang of Beijing (CN) for international business machines corporation
IPC Code(s): G06F11/36
Abstract: embodiments of the invention are directed to computer-implemented methods of analyzing a web-based software application. a non-limiting example of the computer implemented method includes generating, using a processor system, a set of to-be-tested element-event pairs of the web-based software application. a set of compatibility tests is received at the processor system, where the set of compatibility tests is operable to perform compatibility testing of a corresponding set of element-event pairs. a comparison is performed between the set of to-be-tested element-event pairs and the corresponding set of element-event pairs. a compatibility testing recommendation is generated based at least in part on a result of the comparison.
Inventor(s): Daniel Waddington of Morgan Hill CA (US) for international business machines corporation, MOSHIK HERSHCOVITCH of Tel-Aviv (IL) for international business machines corporation
IPC Code(s): G06F12/121, G06F9/455
Abstract: according to an aspect, a computer-implemented method includes operating a program on a virtual machine on a first device having a local cache memory. based on a determination that an epoch timer has not expired, aspects include writing one or more updates to the local cache memory and transmitting evicted items from the local cache memory to a shared memory device that is separate from the first device. based on a determination that an epoch timer has expired, aspects include flushing the local cache memory to the shared memory device, transmitting a virtual cpu state of the virtual machine to the shared memory device, and resetting the epoch timer.
Inventor(s): Peng Hui Jiang of Beijing (CN) for international business machines corporation, Jun Su of Beijing (CN) for international business machines corporation, Guang Han Sui of Beijing (CN) for international business machines corporation, Di Li Hu of Beijing (CN) for international business machines corporation
IPC Code(s): G06F16/23
Abstract: method, computer program product, and computer system are provided. traffic is collected against a nosql database by an activity collector. a database transaction log is periodically extracted and analyzed. the collected traffic and the analyzed database transaction log are input to building a knowledge base of database access patterns. current traffic is captured and used to compute an activity threshold. traffic is directed to a workload processor based on the activity threshold. traffic is directed to an intensive insert/update/delete (iud) processor in response to the activity threshold exceeding a configured threshold. a plurality of temporary shards is generated along with an adaptive key and adaptive index in the plurality of temporary shards. the intensive iud processor traffic is re-directed to the plurality of temporary shards while the activity threshold exceeds the configured threshold.
Inventor(s): Tarun Tater of Mundwa (IN) for international business machines corporation, Jaydeep Sen of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F16/33, G06F40/205, G06F40/263
Abstract: one or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to a process to facilitate multi-lingual query interpretation. a system can comprise a memory that stores computer executable components, and a processor that executes the computer executable components stored in the memory, wherein the computer executable components can comprise an annotation component that generates one or more language invariant signals, an interpretation component that generates a complete query intent using the one or more language invariant signals, and a translation component that processes the complete query intent to an executable backend query to facilitate multi-lingual query interpretation. in one or more embodiments, the translation component can be operatively connected with the interpretation component to generate a zero-shot transfer of the one or more language invariant signals.
Inventor(s): Gandhi Sivakumar of Bentleigh (AU) for international business machines corporation, Smitkumar Narotambhai Marvaniya of BANGALORE (IN) for international business machines corporation, Vijay Ekambaram of Chennai (IN) for international business machines corporation, Luke Peter Macura of Lucas (AU) for international business machines corporation
IPC Code(s): G06F16/35, G06F16/31, G06F16/332, G06F40/30
Abstract: an embodiment includes analyzing text content of a user query to identify via natural language processing (nlp) a query topic. the embodiment maps the query topic to a topic cluster at a node of a hierarchical model of a text database. the embodiment generates query demand data indicative of demand for the topic cluster based on user queries. the embodiment identifies the topic cluster as a topic-cache candidate based on the query demand data. the embodiment compares an amount of memory required for storing text associated with the first topic cluster to available cache memory. the embodiment caches the text of the topic cluster candidate upon determining that there is sufficient available cache memory space.
Inventor(s): Zachary A. Silverstein of Georgetown TX (US) for international business machines corporation, Sonya Leech of Trim (IE) for international business machines corporation, Lisa Ann Cassidy of Dublin (IE) for international business machines corporation, Kelley Anders of East New Market MD (US) for international business machines corporation
IPC Code(s): G06F16/9535
Abstract: a computer-implemented method for filtering search engine results for a user is provided. the method includes maintaining a filtration layer that is opted into by a search engine and a client device. the method further includes building a user search interaction model, operatively coupled to the filtration layer, based on a user's profile and historic search results by performing a topic analysis on a user's interactions with the historic search results and selecting a subset of relevant topics based on respective amounts of user interaction. the user interaction includes interactions on a plurality of different devices. the method also includes filtering search results produced for a particular user search query on the client device using the user search interaction model and the filtration layer.
Inventor(s): BRIAN GILLIKIN of Washington DC (US) for international business machines corporation, Zachary A. Silverstein of Georgetown TX (US) for international business machines corporation, Trinette Ann Brownhill of Montgomery TX (US) for international business machines corporation, Hua Ni of Chantilly VA (US) for international business machines corporation
IPC Code(s): G06F21/31
Abstract: aspects of the present disclosure relate to use-based security challenge authentication. usage frequency metrics for features of an electric device can be collected over time. a set of critical features can be determined based on the collected usage frequency metrics, where each critical feature has a usage frequency exceeding a usage frequency threshold. a determination can be made whether a condition is met for use-based authentication. in response to determining that the condition is met for use-based authentication, a use-based security challenge can be generated using a critical feature, the use-based security challenge based on use frequency of the critical feature. the generated use-based security challenge can be presented to the user. a response to the use-based security challenge can be received. a sufficiency of the response to the use-based security challenge can be determined. access to the electronic device can be authorized based on a sufficiency of the response.
Inventor(s): Su LIU of Austin TX (US) for international business machines corporation, Boyi TZEN of Taipei City (TW) for international business machines corporation, Fan YANG of Beijing (CN) for international business machines corporation, Saraswathi Sailaja PERUMALLA of Visakhapatnam (IN) for international business machines corporation
IPC Code(s): G06F21/55, G06F21/56
Abstract: provided are a computer program product, system, and method for detection of a homoglyph attack in code reviewed in an augmented reality display. a determination is made whether a line of code of source code includes a non-coding script character in a non-coding script that is a homoglyph of a coding script character in a coding script as indicated in a homoglyph pair. valid statements in a computer language in which the source code is written are formed from characters in the coding script and not from characters in the non-coding script. in response to determining that the line of code includes the non-coding script character in the homoglyph pair, transmitting information on the homoglyph pair to cause the augmented reality display to render information on indication of the homoglyph.
Inventor(s): Dong Hui Liu of Beijing (CN) for international business machines corporation, Peng Hui Jiang of Beijing (CN) for international business machines corporation, Jing Lu of Beijing (CN) for international business machines corporation, Jia Yu of BEIJING (CN) for international business machines corporation, Jun Su of Beijing (CN) for international business machines corporation, Xiao Yan Tang of BEIJING (CN) for international business machines corporation, Yong Yin of BEIJING (CN) for international business machines corporation
IPC Code(s): G06F21/56, G06F21/51
Abstract: an embodiment includes generating a caller list of callers that issue requests for calling a designated program at runtime. the embodiment also includes generating an authorized caller list of authorized callers allowed to call the designated program, wherein the authorized callers are selected from among callers on the caller list. the embodiment also includes generating an authorization key for each of the authorized callers that the designated program will require as a condition for completing call requests.
Inventor(s): Itai GORDON of Modiin (IL) for international business machines corporation, Shlomit Avrahami Tomer of Jerusalem (IL) for international business machines corporation, Ofer Haim of Rosh Ha'ain (IL) for international business machines corporation, Miriam NIZRI of Jerusalem (IL) for international business machines corporation
IPC Code(s): G06F21/62, G06F16/21, G06N5/02
Abstract: a computer-implemented method, a computer system and a computer program product select enterprise assets for migration to open cloud storage. the method includes identifying an asset on a server. the method also includes determining whether the asset contains sensitive information. the method further includes obtaining a migration cost for the asset based on asset attributes. in addition, the method includes calculating a migration score for the asset based on whether the asset contains the sensitive information, access rules for the asset, an asset handling history, and the migration cost. lastly, the method includes selecting the asset for migration to open cloud storage when the migration score of the asset is above a threshold.
Inventor(s): Shun Zhang of San Mateo CA (US) for international business machines corporation, Xin Zhang of Chappaqua NY (US) for international business machines corporation, Shaoze Fan of East Newark NJ (US) for international business machines corporation, Ningyuan Cao of Countryside IL (US) for international business machines corporation, Jing Li of Clifton NJ (US) for international business machines corporation, Xiaoxiao Guo of Mountain View CA (US) for international business machines corporation, Chuang Gan of Cambridge MA (US) for international business machines corporation
IPC Code(s): G06F30/398
Abstract: a method, system, and computer program product for circuit design automation. the method identifies a set of circuit components for a proposed circuit design. a subset of circuit components is selected to generate an initial topology for the proposed circuit design. a set of subsequent topologies are iteratively generated by a heuristic search algorithm based on the subset of circuit components and the initial topology. a set of valid topologies of the set of subsequent topologies are determined by a circuit simulator based on the subset of circuit components and a set of connections within the set of subsequent topologies. the method generates the proposed circuit design from the set of valid topologies.
Inventor(s): Avinash Tukaram Mane of Chinchwad (IN) for international business machines corporation, Ratnakar Behera of Bangalore (IN) for international business machines corporation, Sanket Jain of Gurgaon (IN) for international business machines corporation, ZHENG XIE of Clontarf (IE) for international business machines corporation, Krishnasuri Narayanam of Bangalore (IN) for international business machines corporation, JOY PATRA of Dublin (IE) for international business machines corporation
IPC Code(s): G06F40/20, G06F40/35
Abstract: method, computer program product, and computer system are provided. questions are extracted from a chat in real-time during an online meeting and are aggregated into groups of duplicate questions. the groups are presented to a subset of attendees whose question is in the group. feedback is received and applied to the group from the subset of attendees. whether a question is answerable is predicted. for answerable questions an amount of time to answer the question is predicted. the answerable questions are sequenced, filtered, prioritized, and presented to an attendee interface and a presenter interface.
Inventor(s): Sathya Santhar of Ramapuram (IN) for international business machines corporation, Sarbajit K. Rakshit of KOLKATA (IN) for international business machines corporation, Sridevi Kannan of Chennai (IN) for international business machines corporation, Samuel Mathew Jawaharlal of CHENNAI (IN) for international business machines corporation
IPC Code(s): G06F40/30, G06F40/20
Abstract: a method, computer program, and computer system are provided for text summarization that maintains emotional content. data corresponding to text to be summarized and a target emotion to be maintained in the text to be summarized is received. the target emotion is encoded as an emotion probability vector. one or more words that correspond to the target emotion that is encoded in the emotion probability vector are identified from a dictionary. a text summary to be associated with the text to be summarized is generated based on the one or more identified words.
Inventor(s): Kunal Sawarkar of Franklin Park NJ (US) for international business machines corporation, Shivam Raj Solanki of Austin TX (US) for international business machines corporation
IPC Code(s): G06F40/35, G06F40/166, G06F40/279, G06F40/40
Abstract: one or more systems, devices, computer program products and/or computer-implemented methods provided herein relate to determining veracity of answers generated by machine comprehension question and answer models. according to an embodiment, a machine comprehension component can generate a first answer to a query by extracting the first answer from a passage of text corpus. the text corpus alteration component can alter the text corpus one or more times to produce one or more altered text corpora. the machine comprehension component can further extract one or more additional answers to the query from the altered text corpora. a comparison component can determine a veracity score for the first answer based on one or more comparisons of the first answer with the one or more additional answers.
Inventor(s): CHIH-YUAN LIN of New Taipei City (TW) for international business machines corporation, Jin Shi of Ningbo (CN) for international business machines corporation, Shu-Chih Chen of New Taipei City (TW) for international business machines corporation, PEI-YI LIN of New Taipei City (TW) for international business machines corporation, Chao Yuan Huang of Taipei (TW) for international business machines corporation
IPC Code(s): G06F40/47, G06F40/49, G06F40/58
Abstract: translating applications to a target language includes extracting program integrated information (pii) to be translated and creating translation context datasets based on interpretation of accessibility information associated with particular strings of pii. translation pairs include pii and corresponding context datasets for context-based translation of application components. a two-stage index contains pii strings for first stage lookup and context datasets for distinguishing duplicate pii strings as a second stage lookup. real-time translation is facilitated by the two-stage index, which is established by translation pairs and resulting translations.
Inventor(s): Songtao Lu of White Plains NY (US) for international business machines corporation, Xiaodong Cui of Chappaqua NY (US) for international business machines corporation, Mark S. Squillante of Greenwich CT (US) for international business machines corporation, Brian E.D. Kingsbury of Cortlandt Manor NY (US) for international business machines corporation, Lior Horesh of North Salem NY (US) for international business machines corporation
IPC Code(s): G06N3/08
Abstract: decentralized bilevel optimization techniques for personalized learning over a heterogenous network are provided. in one aspect, a decentralized learning system includes: a distributed machine learning network with multiple nodes, and datasets associated with the nodes; and a bilevel learning structure at each of the nodes for optimizing one or more features from each of the datasets using a decentralized bilevel optimization solver, while maintaining distinct features from each of the datasets. a method for decentralized learning is also provided.
Inventor(s): Raghuveer Prasad Nagar of Kota (IN) for international business machines corporation, Prashant Pillai of Bangalore (IN) for international business machines corporation, Suvojyoti Sinha Ray of Hooghly (IN) for international business machines corporation, Pradeep Kumar Katherapally of Yemmiganur (IN) for international business machines corporation
IPC Code(s): G06N3/08, G06N3/04
Abstract: a computer-implemented process for training a neural network includes the following operations. return data received from a return channel is evaluated against a threshold. based upon the threshold being satisfied, the return data is validated, and the return data is cognitive processed to generate a return insight. using the neural network and based upon the return insight, a corrective action is generated. the neural network is trained using feedback generated based upon the corrective action. the threshold is then updated using the neural network.
Inventor(s): Neerju Gupta of Chelmsford MA (US) for international business machines corporation, Namit Kabra of Hyderabad (IN) for international business machines corporation, Yannick Saillet of Stuttgart (DE) for international business machines corporation
IPC Code(s): G06N5/02, G06F40/58
Abstract: an embodiment for monitoring machine learning models to detect and rectify model drift using governance. the embodiment may receive a plurality of machine learning models and register the plurality of machine learning models to a governance dashboard. the embodiment may automatically monitor the received plurality of machine learning models to identify factors used by each of the received plurality of machine learning models and generate corresponding clusters of similar machine learning models. the embodiment may automatically detect an incorrect decision made by a target machine learning model and then automatically calculate a correlation score between the target machine learning model and machine learning models within an associated corresponding cluster of similar machine learning models. the embodiment may, in response to detecting a correlation score above a threshold, automatically determine and output a cluster reinforcement recommendation.
Inventor(s): Devin Underwood of Bronx NY (US) for international business machines corporation, Jiri Stehlik of New York NY (US) for international business machines corporation, Oliver Dial of Yorktown Heights NY (US) for international business machines corporation, David Lokken-Toyli of White Plains NY (US) for international business machines corporation
IPC Code(s): G06N10/40, H01L27/18, H01L39/04, H01L39/06, H01L39/12
Abstract: a quantum circuit device includes a qubit chip including a plurality of qubits and a plurality of flux tunable couplers. a plurality of fixed frequency qubits are arranged in in a lattice structure, wherein each pair of the plurality of fixed frequency qubits is coupled to one flux tunable coupler. a wiring layer is coupled to the qubit chip, and the wiring layer includes a loop constructed of a superconducting material that is inductively coupled to the flux tunable couplers. a flux bias line is constructed of a superconducting material that is different than the superconducting material of the loop, wherein the flux bias line is inductively coupled to both the loop and the flux tunable couplers.
Inventor(s): Dennis Wei of Sunnyvale CA (US) for international business machines corporation, Rahul Nair of Dublin (IE) for international business machines corporation, Amit Dhurandhar of Yorktown Heights NY (US) for international business machines corporation, Kush Raj Varshney of Chappaqua NY (US) for international business machines corporation, Elizabeth Daly of Dublin (IE) for international business machines corporation, Moninder Singh of Farmington CT (US) for international business machines corporation, Michael Hind of Cortlandt Manor NY (US) for international business machines corporation
IPC Code(s): G06N20/00
Abstract: techniques regarding determining sufficiency of one or more machine learning models are provided. for example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. the system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in memory. the computer executable components can comprise a measurement component that measures maximum deviation of a supervised learning model from a reference model over a certification set and an analysis component that determines sufficiency of the supervised learning model based at least in part on the maximum deviation.
Inventor(s): Sumanta Mukherjee of Bangalore (IN) for international business machines corporation, Bhanukiran Vinzamuri of Long Island City NY (US) for international business machines corporation, Vikas C. Raykar of Bangalore (IN) for international business machines corporation, Arindam Jati of Bengaluru (IN) for international business machines corporation, Nupur Aggarwal of Bangalore (IN) for international business machines corporation
IPC Code(s): G06N20/00
Abstract: deriving insights from time series data can include receiving subject matter expert (sme) input characterizing one or more aspects of a time series. a model template that specifies one or more components of the time series can be generated by translating the sme input using a rule-based translator. a machine learning model based on the model template can be a multilayer neural network having one or more component definition layers, each configured to extract one of the one or more components from time series data input corresponding to an instantiation of the time series. with respect to a decision generated by the machine learning model based on the time series data input, a component-wise contribution of each of the one or more components to the decision can be determined. an output can be generated, the output including the component-wise contribution of at least one of the one or more components.
Inventor(s): Srini Bhagavan of LENEXA KS (US) for international business machines corporation, Prasanna Alur Mathada of BANGALORE (IN) for international business machines corporation, Hrishikesh Sujaya Kumar of BANGALORE (IN) for international business machines corporation, Thuan D. Ngo of San Jose CA (US) for international business machines corporation
IPC Code(s): G06Q10/06, G06F11/32
Abstract: an example operation may include one or more of ingesting data records from a plurality of external data sources via a plurality of api calls, generating a plurality of digital footprints for a plurality of users, respectively, which have access to a common finite space, wherein each digital footprint includes a respective health value of a respective user generated based on ingested data records of the user, identifying a user from among the plurality of users which is about to enter the common finite space, in response to identifying the user, determining a cumulative safety value for the common finite space based on the digital footprint of the identified user and a digital footprint of one or more other users already present within the common finite space, and transmitting an alert to a computing system based on the determined cumulative safety value for the common finite space.
Inventor(s): Elisabeth Claire Paulson of Cambridge MA (US) for international business machines corporation, Ashish Jagmohan of Irvington NY (US) for international business machines corporation, Ajay Ashok Deshpande of White Plains NY (US) for international business machines corporation, Pavithra Harsha of White Plains NY (US) for international business machines corporation, Ali Koc of White Plains NY (US) for international business machines corporation, Krishna Chaitanya Ratakonda of Yorktown Heights NY (US) for international business machines corporation, Ramesh Gopinath of Millwood NY (US) for international business machines corporation
IPC Code(s): G06Q10/0875, G06Q30/0601
Abstract: an example operation may include one or more of acquiring, by a retailer node, an inventory data from a supplier node over a blockchain network, receiving, by the retailer node, outstanding orders data of the supplier node, generating, by the retailer node, an order distribution policy based on the inventory data and the outstanding orders data, and executing a smart contract to order goods from the supplier node based on the ordering policy.
Inventor(s): Gero Dittmann of Zürich (CH) for international business machines corporation, Angelo De Caro of Zürich (CH) for international business machines corporation
IPC Code(s): G06Q20/38, G06Q20/40
Abstract: a disclosed technique enables a tree of transactions between entities which may be a first entity and a second entity. the technique may be implemented at a transaction recipient, which can be one of the entities or an external actor, such as a certifier. the transaction recipient accesses two transactions, including a first and second transaction, and two respective secrets, including a first and second secret. the first transaction originates from the first entity, while the second transaction originates from the second entity. the first and second transaction are obfuscated based on the first secret and the second secret, respectively. the first transaction is logically connected to the second transaction. the transaction recipient further de-obfuscates the two transactions using the two respective secrets, and cryptographically signs at least a part of the second transaction to obtain a signature, prior to allowing the second entity to access the obtained signature.
Inventor(s): Satisha C Honnavalli of Bangalore (IN) for international business machines corporation, Bharat Sarjerao Khade of Bangalore (IN) for international business machines corporation, Sai Nikhil Javvaji of Dhone (IN) for international business machines corporation, Raghuveer Prasad Nagar of Kota (IN) for international business machines corporation
IPC Code(s): G06Q30/06, G06Q30/02
Abstract: a computer-implemented method for resolving a potential loss of sale, is disclosed. the computer-implemented method includes determining a potential lost sale and an item associated with the potential lost sale. the computer-implemented method further includes determining a reason for the potential lost sale of the item. the computer-implemented method further includes determining one or more substitute items for the item based, at least in part, on the determined reason for the potential lost sale of the item. the computer-implemented method further includes presenting the one or more determined substitute items to a user.
Inventor(s): Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Martin G. Keen of Cary NC (US) for international business machines corporation, Alexander Reznicek of Troy NY (US) for international business machines corporation, Bahman Hekmatshoartabari of White Plains NY (US) for international business machines corporation
IPC Code(s): G06T17/00, G06T5/00, G06T19/20
Abstract: in an approach to improve the generation of a virtual object in a three-dimensional virtual environment, embodiments of the present invention identify a virtual object to be generated in a three-dimensional virtual environment based on a natural language utterance. additionally, embodiments generate the virtual object based on a clip-guided generative latent space (clip-gls) analysis, and monitor usage of the generated virtual object in the three-dimensional virtual space. moreover, embodiments infer human perception data from the monitoring, and generate a utility score for the virtual object based on the human perception data.
Inventor(s): Nuo XU of Hangzhou (CN) for international business machines corporation, Yuan LI of Ningbo (CN) for international business machines corporation, Shen QI of Ningbo (CN) for international business machines corporation, Jia MAO of Shanghai (CN) for international business machines corporation
IPC Code(s): G06T19/00, G06K7/10, G06T15/20
Abstract: techniques are provided for performing an rfid-based localization and mapping of an environment. in one embodiment, the techniques involve generating identifying information of a first virtual object based on a rfid tag scan, retrieving a first virtual object model or a first object model data based on the identifying information of the first virtual object, generating display data of the first virtual object model or the first object model data relative to a position of an augmented reality system, and rendering the first virtual object model or the first object model data on a display based on the display data.
Inventor(s): Jana H. Jenkins of Raleigh NC (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Tushar Agrawal of West Fargo ND (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G06T19/00, G06F3/01, G06T19/20, G06V10/74, G06V40/20
Abstract: according to one embodiment, a method, computer system, and computer program product for physical object selection within an augmented-reality environment is provided. the present invention may include identifying a plurality of physical objects in a camera feed from an augmented reality device; responsive to detecting one or more gestures of a user within the camera feed, rendering one or more virtual lines extrapolating from one or more fingers of the user within the augmented reality environment; and responsive to the user selecting a physical object of the plurality of physical objects, performing one or more actions with respect to the selected physical object.
Inventor(s): Mauro Marzorati of Lutz FL (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Carolina Garcia Delgado of Zapopan (MX) for international business machines corporation
IPC Code(s): G06V10/22, G06T11/20, G06V10/82, G06V20/20
Abstract: according to one embodiment, a method, computer system, and computer program product for selective image processing. the embodiment may include receiving a digital image for selective image processing. the embodiment may include identifying a context of the selective image processing. the embodiment may include performing object detection within the received digital image to identify one or more depicted objects based on the identified context. the embodiment may include overlaying, on at least one portion of the received digital image, one or more bounding boxes which encompass relative positions of the identified one or more depicted objects. the embodiment may include performing the selective image processing exclusively within the one or more overlaid bounding boxes.
Inventor(s): Lam Minh Nguyen of Ossining NY (US) for international business machines corporation, Wang Zhang of Cambridge MA (US) for international business machines corporation, Subhro Das of Cambridge MA (US) for international business machines corporation, Pin-Yu Chen of White Plains NY (US) for international business machines corporation, Alexandre Megretski of Acton MA (US) for international business machines corporation, Luca Daniel of Cambridge MA (US) for international business machines corporation
IPC Code(s): G06V10/764, G06V10/774
Abstract: a computer implemented method for certifying robustness of image classification in a neural network is provided. the method includes initializing a neural network model. the neural network model includes a problem space and a decision boundary. a processor receives a data set of images, image labels, and a perturbation schedule. images are drawn from the data set in the problem space. a distance from the decision boundary is determined for the images in the problem space. a re-weighting value is applied to the images. a modified perturbation magnitude is applied to the images. a total loss function for the images in the problem space is determined using the re-weighting value. a confidence level of the classification of the images in the data set is evaluated for certifiable robustness.
Inventor(s): Ying Li of Shanghai (CN) for international business machines corporation, Fang Lu of Shanghai (CN) for international business machines corporation, Yuan Yuan Gong of Shanghai (CN) for international business machines corporation, Wen Ting Li of Shanghai (CN) for international business machines corporation, Shi Hui Gui of Shanghai (CN) for international business machines corporation, Xiao Feng Ji of Shanghai (CN) for international business machines corporation
IPC Code(s): G06V10/774, G06V10/10, G06V10/26, G06V10/764, G06V20/70
Abstract: at least one computer processor can replace visual words of an unsupervised machine learning classification model with visual objects of an image. at least two co-occurring single visual objects adjacent to each other in pixels of the image can be combined to obtain a compound visual object. the unsupervised machine learning classification model can be augmented to model the image as a mixture of subjects, where each subject is represented through placements of the visual objects in a mixture of concentric spheres centering on a mixture of intersections on a mixture of horizontal layers. at least one processor can learn latent relationships between the placements of the visual objects in a three-dimensional space depicted in the image and image semantics. learning the latent relationships trains the unsupervised machine learning classification model to perform image subject classification through the placements of the visual objects in a new image.
Inventor(s): Zhong Fang YUAN of Xi'an (CN) for international business machines corporation, Tong LIU of Xi'an (CN) for international business machines corporation, Yi Chen ZHONG of Shanghai (CN) for international business machines corporation, Xiang Yu YANG of Xi'an (CN) for international business machines corporation, Guan Chao LI of Shanghai (CN) for international business machines corporation
IPC Code(s): G06V30/148, G06V10/774, G06V10/82, G06V30/182
Abstract: provided are a computer program product, system, and method for training and using a vector encoder to determine vectors for sub-images of text in an image to subject to optical character recognition. a vector encoder is trained to encode images representing text into vectors in a vector space. vectors of images representing similar text have a high degree of cohesion in the vector space. vectors of images representing dissimilar text have a low degree of cohesion in the vector space. an input image is processed to determine sub-images of the input image that bound text represented in the input image. the sub-images are inputted to the vector encoder to output sub-image vectors. the vector encoder generates a search vector for search text. optical character recognition is applied to at least one region of the input image including the sub-images having sub-image vectors matching the search vector.
Inventor(s): Scott CARRIER of New Hill NC (US) for international business machines corporation, Ritwik RAY of Apex NC (US) for international business machines corporation, Jonathan Chapin RAND of Ann Arbor MI (US) for international business machines corporation, Jothilakshmi SIRANGIMOORTHY of Canton MI (US) for international business machines corporation, Hui WANG of Ann Arbor MI (US) for international business machines corporation, Robert FREDENBURG of Kalamazoo MI (US) for international business machines corporation
IPC Code(s): G06V30/412, G06F3/0482, G06F40/237, G06F40/40, G06V30/416
Abstract: provided are a computer program product, system, and method for pre-processing a table in a document for natural language processing (nlp). a graphical user interface (gui) provides a representation of table items in a table in a document including a set of a main element comprising an entity whose value is to be extracted, a conditional element that refines the entity, and a value element comprising a value for the entity. graphical controls are rendered in the gui to enable a user to select an element from the table to be the main element, conditional element, and value element. the set of the main element, conditional element, and value element are updated with the user selected element to form a modified set. the modified set of the main element, conditional element, and the value element are provided to an nlp engine to perform natural language processing.
Inventor(s): Kevin W. Brew of Niskayuna NY (US) for international business machines corporation, Michael S. Gordon of Chappaqua NY (US) for international business machines corporation, Mattias Fitzpatrick of Mount Kisco NY (US) for international business machines corporation, Brian Paul Gaucher of Brookfield NY (US) for international business machines corporation
IPC Code(s): G08B21/10, G16Y20/10
Abstract: described are techniques for corroborating anomalous behavior. the techniques include training devices included in an internet of things (iot) mesh network to independently identify occurrences of anomalous behavior in a proximate physical environment. the techniques further include receiving event data from at least a portion of the devices in the iot mesh network corresponding to a time window, where the event data reports occurrences of at least one type of anomalous behavior. the techniques further include corroborating the at least one type of anomalous behavior to determine that the occurrences of the at least one type of anomalous behavior indicate an anomalous event that meets a reporting threshold for providing notice of the anomalous event. the techniques further include generating a notification regarding the anomalous event.
Inventor(s): Atul Mene of Morrisville NC (US) for international business machines corporation, Tushar Agrawal of West Fargo ND (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Martin G. Keen of Cary NC (US) for international business machines corporation
IPC Code(s): G08G1/005, G08G1/16
Abstract: provided is a computer-implemented method, system, and computer program product for displaying information to a pedestrian using a visual indicator. a processor may detect that a vehicle is approaching a pedestrian. the processor may determine that the pedestrian is unable to see the approaching vehicle. the processor may display an indication that the vehicle is approaching the pedestrian on an object the pedestrian can currently view.
Inventor(s): Raghuveer Prasad Nagar of Kota (IN) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Manjit Singh Sodhi of Bangalore (IN) for international business machines corporation, Sidharth Ullal of Chennai (IN) for international business machines corporation
IPC Code(s): G09B5/06, G06F3/0354, G06F3/0482
Abstract: a system and method are used to record and present a training video for a software component. the method displays the video recording. the video recording comprises: a display element of the software component, and first recorder activity data (frad) of recorder user interface (ui) input activity data (ruiiad) at a frad time with video frame data of the video recording. the method further comprises receiving, during the displaying, viewer ui actions from a ui of the viewing device and converting them to viewer ui input activity data based on viewer interactions with the display element of the software component. then, first viewer activity data (fvad) is determined at a fvad time of the video frame that corresponds to the frad, where the frad time and the fvad time differ. responsive to the determining, the method moves the video recording from the fvad time to the frad time.
Inventor(s): Iain Furneaux of Witley (GB) for international business machines corporation
IPC Code(s): G09B19/00, G09B5/02
Abstract: the invention provides for a method, computer program product, and computer system for a training platform for training a user on an application. the method provides training content to a training platform interface at a user browser, wherein the training content includes instructions for a user on interaction with an application and provides access to an application instance at the training platform interface for user interaction with the application instance. the method further provides a session of an application instance hosted by an application node for the duration of a training session. the method may further determine a training content and an application from user input received at the user browser and broadcasting a message to find a free application instance of the application. the method may further select an application instance from one or more responses from application nodes based on defined selection factors.
Inventor(s): Wei Jun Zheng of Shanghai (CN) for international business machines corporation, Shi Kun Li of Shanghai (CN) for international business machines corporation, Shuai Cao of Shanghai (CN) for international business machines corporation, Fan Xiao Xin of Shanghai (CN) for international business machines corporation, Ying Li of Shanghai (CN) for international business machines corporation
IPC Code(s): G10L21/0272, G10L15/26, G10L25/78
Abstract: an embodiment includes identifying, during a video conference attended by a first attendee, other attendees of the video conference. the embodiment renders a virtual meeting environment including virtual representations of the other attendees, where the rendering includes accessing relationship characteristic data indicative of relationships between the first attendee and other attendees. the embodiment calculates positions for virtual representations of the other attendees in the first attendee's virtual field of view based on the relationship characteristic data. the embodiment also detects simultaneous speech from two of the other attendees and, in response, directs the individual speech from each of the other attendees to respective audio channels.
Inventor(s): Tushar Agrawal of West Fargo ND (US) for international business machines corporation, Martin G. Keen of Cary NC (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G11B27/031
Abstract: according to one embodiment, a method, computer system, and computer program product for selectively recording meetings is provided. the embodiment may include initiating a digital meeting. the embodiment may also include determining two or more rule sets, including one or more local rule sets, for selectively recording the digital meeting, wherein each rule set includes one or more rules. the embodiment may further include recording one or more recordings of the digital meeting according to each local rule set.
Inventor(s): Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation
IPC Code(s): H01L21/768, H01L23/522
Abstract: a semiconductor device and formation thereof. the semiconductor device includes a first via in a metal layer, wherein the first via is a single damascene structure. the semiconductor device further includes a second via in the metal level, wherein the second via is a dual damascene structure.
Inventor(s): Chen Zhang of Guilderland NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Heng Wu of Santa Clara CA (US) for international business machines corporation, Min Gyu Sung of Latham NY (US) for international business machines corporation
IPC Code(s): H01L21/768, H01L21/8234, H01L23/528
Abstract: a semiconductor structure is presented including a backside contact of a nanosheet transistor positioned on a silicon (si) layer of a wafer and a dielectric liner disposed between the backside contact and the si layer such that the dielectric liner is located below gate spacers of the nanosheet transistor. the backside contact is closer to a backside of the wafer than a frontside of the wafer. the dielectric liner is vertically aligned with the gate spacers and the dielectric liner is vertically aligned with inner spacers of a nanosheet stack of the nanosheet transistor.
Inventor(s): Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Kisik Choi of Watervliet NY (US) for international business machines corporation, Brent A. Anderson of Jericho VT (US) for international business machines corporation
IPC Code(s): H01L23/48, H01L21/8234, H01L29/06, H01L29/08, H01L29/66, H01L29/775
Abstract: a semiconductor device includes first source/drain (s/d) epitaxy and a second s/d epitaxy and a gate contact. the device also includes a back end of the line (beol) layer connected electrically connected to the first s/d epitaxy and the gate contact on a top side of the device and a wafer that carries the beol layer and is on the top side of the device. the device also includes a backside trench epitaxy formed through and contacting portions of the second s/d epitaxy and a backside power distribution network electrically coupled to the backside trench epitaxy and disposed on the bottom of the device.
Inventor(s): Tao Li of Slingerlands NY (US) for international business machines corporation, Sagarika Mukesh of ALBANY NY (US) for international business machines corporation, Liqiao Qin of ALBANY NY (US) for international business machines corporation, Prabudhya Roy Chowdhury of ALBANY NY (US) for international business machines corporation, Kisik Choi of Watervliet NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L23/48, H01L21/768, H01L21/8234, H01L29/08
Abstract: a semiconductor device includes a backside power rail; a transistor source/drain structure that has a backside facing the backside power rail and has a frontside facing away from the backside power rail; and a via disposed between and electrically connecting the backside power rail and the source/drain structure. the via includes a buried portion that is disposed between the backside power rail and the backside of the transistor source/drain structure. a part of the buried portion overlaps and contacts at least a part of the backside of the source/drain structure. the via also includes a side portion that is electrically connected with the buried portion and extends along a vertical side of the source/drain structure between the frontside and the backside; and a top portion that is electrically connected with the side portion and covers at least a part of the frontside of the source/drain structure.
Inventor(s): Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L23/522, H01L23/00, H01L23/528, H01L25/065
Abstract: a semiconductor structure includes a power distribution structure disposed on a first wafer, an interconnect structure disposed on the first wafer and a second wafer, and at least one decoupling capacitor connected between the power distribution structure and the interconnect structure.
Inventor(s): Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Brent A. Anderson of Jericho VT (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Reinaldo Vega of Mahopac NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L23/522, H01L21/768, H01L23/528
Abstract: an interconnect structure for connecting an upper wiring line to a lower wiring line includes a via connecting a lower portion of the upper wiring line with an upper surface of the lower wiring line and a wrap-around via portion formed integrally with the via, the wrap-around portion extending along and electrically contacting a portion of the sides of the lower wiring line.
Inventor(s): Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Reinaldo Vega of Mahopac NY (US) for international business machines corporation, Takashi Ando of Eastchester NY (US) for international business machines corporation, David Wolpert of Poughkeepsie NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L21/02, H01L21/306, H01L23/48, H01L23/522
Abstract: a semiconductor device including an interleaved/nested structure of subtractive interconnects and damascene interconnects. the semiconductor device includes a subtractive-etched interconnect wiring level having subtractive interconnects and a damascene interconnect wiring level having damascene interconnects. the subtractive-etched interconnect wiring level includes first electrodes that have a first potential second electrodes that have a second potential different from the first potential, with the second electrodes generated to interleave the first electrodes. the semiconductor also includes a damascene interconnect wiring level that includes other first electrodes having the first potential, and other second electrodes having the second potential. in the damascene interconnect wiring level, the other second electrodes are also interleaved by the other first electrodes.
Inventor(s): Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Brent A. Anderson of Jericho VT (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Reinaldo Vega of Mahopac NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/522, H01L29/66, H01L29/78
Abstract: a semiconductor device includes: a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks overlying the first via level; a second via level forming a first top jumper overlying the first set of two or more first metallization tracks; and a second metallization track overlying the second via level.
Inventor(s): Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, David Wolpert of Poughkeepsie NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L23/48, H01L23/522
Abstract: embodiments include super via placement in the development of an integrated circuit. aspects of the invention include obtaining a power distribution network for the integrated circuit (ic) ic, wherein the pdn includes a plurality of metal vias each configured to connect adjacent metal layers of a plurality of metal layers. aspects also include placing one or more cells on each metal layer of the ic and identifying a power demand associated with each of the one or more cells. aspects further include updating the pdn, based on the power demand associated with each of the one or more cells, to replace at least two of the plurality of metal vias with a super via that is configured to connect non-adjacent metal layers of the plurality of metal layers.
Inventor(s): Huimei Zhou of Albany NY (US) for international business machines corporation, Terence Hook of Jericho Center VT (US) for international business machines corporation, Junli Wang of Slingerlands NY (US) for international business machines corporation, Miaomiao Wang of Albany NY (US) for international business machines corporation
IPC Code(s): H01L27/02
Abstract: an integrated circuit is presented including a protection diode including a plurality of first gates and a plurality of first source/drain (s/d) contacts and a device under test (dut) including a plurality of second gates and a plurality of second s/d contacts, the dut being electrically connected to the protection diode by either at least one gate contact or at least on ca contact or at least one buried power rail (bpr). the protection diode is electrically connected to the dut by middle-of-line (mol) layers for gate oxide protection before m1 formation.
Inventor(s): Kangguo Cheng of Schenectady NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Min Gyu Sung of Latham NY (US) for international business machines corporation
IPC Code(s): H01L27/092, H01L21/02, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
Abstract: a semiconductor includes a first gaa fet and second gaa fet. the second gaa fet includes a first gate dielectric and second gate dielectric within its gate structure. the first gaa fet includes just the first gate dielectric within its gate structure. the gate dielectric structure of the first gaa fet provides for a nominal or a lesser effective gate dielectric or gate dielectric resistance relative to an effective gate dielectric structure of the second gaa fet. the first gaa fet further includes a first gate conductor within its gate structure and the second gaa fet further includes the first gate conductor and a second gate conductor within its gate structure. the first gate conductor and the second gate conductor are separated by the second gate dielectric.
Inventor(s): Ruqiang Bao of Niskayuna NY (US) for international business machines corporation, Dechao Guo of Niskayuna NY (US) for international business machines corporation, Junli Wang of Slingerlands NY (US) for international business machines corporation, Heng Wu of Santa Clara CA (US) for international business machines corporation
IPC Code(s): H01L27/092, H01L21/02, H01L21/321, H01L21/822, H01L21/8238, H01L23/528, H01L29/06, H01L29/40, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/78
Abstract: a semiconductor device includes a substrate; a set of first transistors positioned on an upper surface of the substrate, each of the set of first transistors comprising a first gate and a first dielectric; an insulating layer positioned on an upper surface of the set of first transistors; and a set of second transistors positioned over the set of first transistors and with the set of first transistors on an upper surface of the insulating layer, each of the set of second transistors having a second gate and a second dielectric; wherein each of the first dielectrics is connected to a sidewall of each of a corresponding first gate; and wherein each of the second dielectrics is connected to the insulating layer.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Julien Frougier of ALBANY NY (US) for international business machines corporation, Min Gyu Sung of Latham NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Juntao Li of Cohoes NY (US) for international business machines corporation
IPC Code(s): H01L27/092, H01L21/8238, H01L23/528, H01L29/06, H01L29/08, H01L29/66, H01L29/775, H01L29/786
Abstract: a cmos apparatus includes a semiconductor substrate that has a frontside and a backside opposite the frontside; a source/drain structure, which is disposed at the frontside of the substrate and has a backside that is adjacent to the substrate and a frontside that is opposite the backside of the source/drain structure; a backside interconnect layer, which is disposed at the backside of the substrate; a backside contact, which penetrates the substrate and electrically connects the source/drain structure to the backside interconnect layer; and a sigma-profiled dielectric structure that insulates first and second sides of the backside contact from the substrate.
Inventor(s): Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Nicolas Jean Loubet of GUILDERLAND NY (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L21/768, H01L23/48, H01L23/528
Abstract: a microelectronic structure including a first transistor including a plurality a first channel layers. a second transistor including a plurality of second channel layers, where the first transistor is located adjacent to the second transistors. a dielectric bar located between the first transistor and the second transistor. a first source/drain of the first transistor is located on a first side of the dielectric bar and a second source/drain of the second transistor is located on a second side of the dielectric bar, where the first side is opposite the second side. a first backside contact connected to the first source/drain, where the first backside contact is in contact with first side of the dielectric bar. a second backside contact connected to the second source/drain, where the second backside contact is in contact with the second side of dielectric bar.
Inventor(s): Kangguo Cheng of Schenectady NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, CHANRO PARK of CLIFTON PARK NY (US) for international business machines corporation, Min Gyu Sung of Latham NY (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L21/8238, H01L29/66, H01L29/775, H01L29/786
Abstract: a lower set of semiconductor channel layers, an upper set of semiconductor channel layers, a lower dielectric layer adjacent to the lower set of semiconductor channel layers, the lower dielectric layer includes a first polarity stress on the lower set of semiconductor channel layers, and an upper dielectric layer adjacent to the upper set of semiconductor channel layers, the lower dielectric layer includes a second polarity stress on the upper set of semiconductor channel layers with opposite polarity stress of the first polarity stress. forming a lower stack of nanosheet layers and an upper stack of nanosheet layers, forming a lower dielectric layer adjacent to the lower stack of nanosheet layers, the lower dielectric layer includes a first polarity stress, and forming an upper dielectric layer adjacent to the upper stack of nanosheet layers, the upper dielectric layer includes a second polarity stress with opposite polarity.
Inventor(s): Kirsten Emilie Moselund of Rüschlikon (CH) for international business machines corporation, Nicolas Jean Loubet of GUILDERLAND NY (US) for international business machines corporation, Bogdan Cezar Zota of Rüschlikon (CH) for international business machines corporation, Shogo Mochizuki of Mechanicville NY (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L21/8238, H01L29/20, H01L29/66, H01L29/775, H01L29/786
Abstract: embodiments of the present invention are directed to the implantation of composite tunnel field effect transistors (tfets) in a nanosheet process. in a non-limiting embodiment of the invention, a first source or drain region is formed having a first composition and a first doping type. a second source or drain region is formed having a second composition and a second doping type opposite the first doping type. a first composite channel structure is formed between the first source or drain region and the second source or drain region. the first composite channel structure includes a first nanosheet trimmed to expose extension portions of the first source or drain region and extension portions of the second source or drain region. the first composite channel structure further includes a first channel epitaxy wrapping around the trimmed first nanosheet. the first channel epitaxy is connected laterally to the extension portions.
Inventor(s): Terence Hook of Jericho Center VT (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L29/423, H01L29/775, H01L29/786
Abstract: semiconductor structures such as, for example, stacked nanosheet devices, having enhanced gate resistance are provided. the enhanced gate resistance is obtained by providing a shunting material pillar in the structure and along a sidewall (or opposing sidewalls) of at least one gate structure. the shunting material pillar has a resistivity that is lower than a resistivity of the gate structure that it is laterally adjacent to.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Kangguo Cheng of Schenectady NY (US) for international business machines corporation, Julien Frougier of ALBANY NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Min Gyu Sung of Latham NY (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L27/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786, H01L29/861
Abstract: a nanosheet diode includes a bookend structure and a central structure. the bookend includes a first semiconductor that is doped as one of the anode and the cathode of the diode, and includes a left block, a right block, and a first stack of spaced-apart nanosheets that horizontally connect the left and right blocks. the central structure includes a second semiconductor that is doped as the other of the anode and the cathode of the diode, and includes a front block, a rear block, and a second stack of nanosheets that are interleaved crosswise into spaces between the first stack of spaced-apart nanosheets and that horizontally connect the front and rear blocks. the bookend structure directly contacts top, bottom, and end surfaces of the second stack of nanosheets of the central structure.
Inventor(s): Sagarika Mukesh of ALBANY NY (US) for international business machines corporation, Tao Li of Slingerlands NY (US) for international business machines corporation, Prabudhya Roy Chowdhury of Albany NY (US) for international business machines corporation, Liqiao Qin of Albany NY (US) for international business machines corporation, Nikhil Jain of Apple Valley MN (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L23/48, H01L27/088, H01L29/08
Abstract: a semiconductor structure is provided that includes a first fet device region including a plurality of first fets, each first fet of the plurality of first fets includes a first source/drain region located on each side of a functional gate structure. a second fet device region is stacked above the first fet device region and includes a plurality of second fets, each second fet of the plurality of second fets includes a second source/drain region located on each side of a functional gate structure. the structure further includes at least one first front side contact placeholder structure located adjacent to one of the first source/drain regions of at least one the first fets, and at least one second front side contact placeholder structure located adjacent to at least one of the second source/drain regions of at one of the second fets.
Inventor(s): Juntao Li of Cohoes NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Nicolas Jean Loubet of Guilderland NY (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L29/786
Abstract: a semiconductor structure comprises a first nanosheet stack comprising one or more first nanosheet channel layers and a first dielectric isolation layer over the one or more first nanosheet channel layers, a second nanosheet stack comprising one or more second nanosheet channel layers and a second dielectric isolation layer over the one or more second nanosheet channel layers, and a gate dielectric layer disposed over a top surface of one of the first dielectric isolation layer and the second dielectric isolation layer.
Inventor(s): Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation, Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L29/417, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775
Abstract: a cmos apparatus includes an n-doped field effect transistor (nfet); and a p-doped field effect transistor (pfet), each of which has a source structure and a drain structure. a common backside drain contact, which is disposed at the backside surface of the nfet and the pfet, electrically connects the nfet drain structure and the pfet drain structure to a backside interconnect layer.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Kangguo Cheng of Schenectady NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Min Gyu Sung of Latham NY (US) for international business machines corporation
IPC Code(s): H01L29/417, H01L23/528, H01L27/092, H01L29/06, H01L29/08, H01L29/40
Abstract: a semiconductor structure having a backside contact structure with increased contact area includes a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions includes a top portion having an inverted v-shaped area. a backside power rail is electrically connected to at least one source/drain region through a backside metal contact. the backside metal contact wraps around a top portion of the at least one source/drain region. a tip of the top portion of the plurality of source/drain regions points towards the backside power rail with the top portion of the at least one source/drain region being in electric contact with the backside metal contact. a first epitaxial layer is in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.
Inventor(s): Alexander Reznicek of Troy NY (US) for international business machines corporation, Takashi Ando of Eastchester NY (US) for international business machines corporation, Jingyun Zhang of Albany NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L29/66, H01L29/08, H01L29/16, H01L29/161, H01L29/78
Abstract: a method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. the method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. the method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.
Inventor(s): Mark K. Hoffmeyer of Rochester MN (US) for international business machines corporation, Matthew Doyle of Chatfield MN (US) for international business machines corporation, Kyle Schoneck of Rochester MN (US) for international business machines corporation, Layne A. Berge of Rochester MN (US) for international business machines corporation, Matthew A. Walther of Rochester MN (US) for international business machines corporation, Thomas W. Liang of Rochester MN (US) for international business machines corporation, John R. Dangler of Rochester MN (US) for international business machines corporation, Jason J. Bjorgaard of Rochester MN (US) for international business machines corporation
IPC Code(s): H01M50/583, H05K1/11
Abstract: a voltage source watchdog comprising a passive device is placed in series between a voltage source and a load. the passive device includes an electromigration (em) joint of known materials that will create an electromigration void after a specified amount of current passes through the em joint. after a known amount of current as passed through, a void is created and a voltage will no longer be sensed, thus providing a sure safety mode situation. when the voltage source is a battery, the battery life may be extended by selectively enabling voltage measurement operations for the proposed watchdog.
Inventor(s): NATHAN LEE DUNFEE of ROCHESTER MN (US) for international business machines corporation, KEVIN O'CONNELL of MANTORVILLE MN (US) for international business machines corporation, CHRISTOPHER M. MARROQUIN of ROCHESTER MN (US) for international business machines corporation, STEPHEN P. MROZ of ROCHESTER MN (US) for international business machines corporation, MARK DAVID PFEIFER of OWATONNA MN (US) for international business machines corporation, KENNETH E. LUBAHN of ORONOCO MN (US) for international business machines corporation, JUSTIN CHRISTOPHER ROGERS of ROCHESTER MN (US) for international business machines corporation
IPC Code(s): H01R12/72
Abstract: an apparatus for guidance and retention of integrated circuit boards includes a first structure configured to receive a first integrated circuit board and guide the first integrated circuit board for coupling to a substrate. the apparatus further includes a second structure configured to be removably coupled to the first structure. the second structure includes a first spring member configured to apply a first compressive force to the first integrated circuit board.
Inventor(s): Nadiya Kochura of Bolton MA (US) for international business machines corporation, Su Liu of Austin TX (US) for international business machines corporation, Hamid Majdabadi of Ottawa (CA) for international business machines corporation, YANG LIANG of Beijing (CN) for international business machines corporation
IPC Code(s): H02J50/90, H02J50/80
Abstract: according to one embodiment, a method, computer system, and computer program product for creating a wireless charging layout. the embodiment may include receiving one or more signals from one or more wireless charger devices within a given space. the embodiment may include identifying a location of a power-consuming electric device within the given space. the embodiment may include identifying respective signal strengths of the one or more wireless charger devices relative to the location of the power-consuming electric device. the embodiment may include retrieving a floor plan of the given space. the embodiment may include creating a signal strength map of the identified respective signal strengths using the retrieved floor pan. the embodiment may include creating an augmented reality (ar) wireless charging layout of the given space based on the signal strength map.
Inventor(s): Michael Karunendra Selvanayagam of Ossining NY (US) for international business machines corporation, Corrado P. Mancini of Hopewell Junction NY (US) for international business machines corporation, David Lokken-Toyli of White Plains NY (US) for international business machines corporation, Gerald W. Gibson of Danbury CT (US) for international business machines corporation, Kathryn Turner Schonenberg of Wappingers Falls NY (US) for international business machines corporation, Shayne Cairns of Valhalla NY (US) for international business machines corporation
IPC Code(s): H03F19/00
Abstract: a method of manufacturing a travelling wave parametric amplifier (twpa) includes forming a superconducting junction on a substrate. trenches are etched away through a metal surface and into a layer of dielectric material. the trenches define a plurality of fingers positioned in an interdigitated arrangement of capacitors defined by a metal and a dielectric material that remains from the etched away metal surface and the layer of dielectric material.
Inventor(s): Arun Paidimarri of South Salem NY (US) for international business machines corporation, WOORAM LEE of BRIARCLIFF MANOR NY (US) for international business machines corporation, Armagan Dascurcu of New York NY (US) for international business machines corporation, BODHISATWA SADHU of Peekskill NY (US) for international business machines corporation, Alberto Valdes Garcia of Chappaqua NY (US) for international business machines corporation, Caglar Ozdag of White Plains NY (US) for international business machines corporation
IPC Code(s): H04B7/08, H04B1/30, H04B7/06
Abstract: systems and methods for operating a beamforming circuit are described. a processor can activate a transmitting element among a plurality of transmitting elements of a beamforming circuit. the processor can activate a receiving element among a plurality of receiving elements of a beamforming circuit. the processor can receive a direct current (dc) signal that represents phase and amplitude of the activated transmitting element and the activated receiving element. the processor can adjust a setting of the beamforming circuit to receive additional dc signals that represent phases and amplitudes of the activated transmitting element and the activated receiving element under the adjusted setting. the processor can determine calibration values for the beamforming circuit based on the dc signal and the additional dc signals.
Inventor(s): Michael Sperling of Poughkeepsie NY (US) for international business machines corporation, Daniel Mark Dreps of Georgetown TX (US) for international business machines corporation, Erik English of Salt Point NY (US) for international business machines corporation, Jieming Qi of Austin TX (US) for international business machines corporation
IPC Code(s): H04L7/00, H04L25/24
Abstract: an integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. the clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. the clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. the divided clock signals are sent at reduced rates compared to the first rate. the clock divider maintains current mode logic properties for the divided clock signals. the first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.
Inventor(s): James William Murdock, IV of Amawalk NY (US) for international business machines corporation, Radha Mohan De of Howrah (IN) for international business machines corporation, Jaymin Desai of Jersey City NJ (US) for international business machines corporation, Suman Patra of KOLKATA (IN) for international business machines corporation, Sujoy Roy of KOLKATA (IN) for international business machines corporation, Mary Diane Swift of Rochester NY (US) for international business machines corporation
IPC Code(s): H04L51/224, G06F40/40, H04L12/18, H04L51/216
Abstract: techniques are described with respect to a system, method, and computer product for generating relevance alerts. an associated method includes analyzing a multi-party discussion based on a generated profile associated with a user and assigning at least one relevance value associated with the user to the multi-party discussion based on the analysis and an amount of multi-party discussion participation associated with the user. the method further includes generating an alert for the user to participate in the multi-party discussion in response to determining the relevance value exceeding a relevance threshold associated with the multi-party discussion.
Inventor(s): Raghuveer Prasad Nagar of Kota (IN) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, RADHA SRINIVASAN of Bangalore (IN) for international business machines corporation, Sidharth Ullal of Chennai (IN) for international business machines corporation
IPC Code(s): H04L9/40, G06F9/451
Abstract: a method includes identifying a cluster of users with a plurality of devices, where each user from the cluster of users is associated with at least one device from the plurality of devices. the method also includes identifying an authorized user from the cluster of users to delegate role assignments to a remaining portion of the cluster of users and receiving, from the authorized user, a first role assignment for a first user from the remaining portion of the cluster of users. in response to receiving, from the first user, an audio command, the method also includes determining whether the first user is authorized to provide the audio command to the intelligent virtual assistant based on the first role assignment. in response to determining the first user is authorized to provide the audio command, the method also includes performing the audio command from the first user.
Inventor(s): Thomas Dürr of Magstadt (DE) for international business machines corporation, Martin Smolny of BOEBLINGEN (DE) for international business machines corporation, Michael Beck of Bad Teinach-Zavelstein (DE) for international business machines corporation, Daniel Pittner of Esslingen am Neckar (DE) for international business machines corporation
IPC Code(s): H04L9/40
Abstract: mechanisms are provided for dispatching requests to service instances based on data storage boundaries. a request specifying an identity is received and dispatched to a service instance of a data storage boundary, where each data storage boundary is defined by a regulation or policy restricting data storage of specific types of data to computing devices within a specified boundary. a feedback response, specifying a target location, is received from the service instance in response to determining that the service instance cannot access the data because the data is associated with a different data storage boundary. a dynamic dispatch rule specifying the identity and the target location is generated and a subsequent request specifying the identity is processed by executing this dynamic dispatch rule to dispatch the subsequent request directly to a service instance associated with the target location.
Inventor(s): Anamitra Bhattacharyya of Chelmsford MA (US) for international business machines corporation, Krishnamohan Dantam of Chelmsford MA (US) for international business machines corporation, Manjunath Makonahalli of Acton MA (US) for international business machines corporation
IPC Code(s): H04L65/401, H04L9/40
Abstract: a computer-implemented method to initiate unplanned interactions for remote workers. the method includes identifying a plurality of user accounts, where each user account is associated with a communication device and a physical location. the method further includes determining a location of each communication device within each physical location. the method also includes generating, for each user account, a collaboration score, where the collaboration scores are based on the location of each communication device. the method includes determining a first collaboration score of a first user account and a second collaboration score of a second user account are above a collaboration threshold. the method also includes initiating, based on the first collaboration score and the second collaboration score being above the threshold, a communication channel between a first communication device and a second communication device.
Inventor(s): Mathews Thomas of Flower Mound TX (US) for international business machines corporation, Sagar Tayal of Ambala City (IN) for international business machines corporation, Utpal Mangla of Toronto (CA) for international business machines corporation, Dinesh C. Verma of New Castle NY (US) for international business machines corporation, SAURABH AGRAWAL of Bangalore (IN) for international business machines corporation
IPC Code(s): H04W12/02, H04W12/08
Abstract: computer-implemented methods for autonomous identification of rouge devices in a communications network are provided. aspects include collecting connection trace data including connection characteristics for each of a plurality of mobile devices in communication with a communications network and aggregating the connection trace data. aspects also include determining performance characteristics for each of a plurality of groups of the plurality of mobile devices, wherein each of the plurality of groups corresponds to mobile devices having a type approval code and comparing the performance characteristics for each of the plurality of groups. based on a determination that the performance characteristics of one of the plurality of groups deviate from the performance characteristics of a remaining set of the plurality of groups by more than a first threshold amount, aspects include designating the type approval code associated with the one of the plurality of groups as a rogue type approval code.
Inventor(s): Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Sudheesh S. Kairali of Kozhikode (IN) for international business machines corporation, Sudhanshu Sekher Sar of Bangalore (IN) for international business machines corporation, Satyam Jakkula of Bengaluru (IN) for international business machines corporation
IPC Code(s): H04W16/04, H04W8/00
Abstract: a method comprising establishing a local communication network among and between a plurality of onboard vehicle computers respectively located in a plurality of vehicles, polling the vicinity of each vehicle to determine a set of qualified mobile device(s) that meet the following criteria: (i) the qualified mobile device is located within one of the vehicles of the plurality of vehicles, (ii) the qualified mobile device is configured and equipped to join the local network, and (iii) the qualified mobile device consents to join the local network, and adding the set of qualified mobile device(s) to the local network.
Inventor(s): Maja Curic of Munich (DE) for international business machines corporation, Sagar Tayal of Ambala City (IN) for international business machines corporation
IPC Code(s): H04W28/08, H04W28/02
Abstract: a computer-implemented method for dynamically reconfiguring a control plane of a radio access network. the computer-implemented method includes generating a self-awareness matrix of a radio access network (ran) that comprises a plurality of e2 nodes, the self-awareness matrix comprises a plurality of records for each respective e2 node from the plurality of e2 nodes, a first record corresponding to a first e2 node comprises, for the first e2 node, one or more attributes of the control plane of the ran, the first e2 node being assigned to a first near-real-time ran intelligent controller (near-rt ric). the method further includes, in response to the first record satisfying a predetermined condition based on the one or more attributes of the control plane reconfiguring the control plane of the ran.
Inventor(s): Maja Curic of Munich (DE) for international business machines corporation, Sagar Tayal of Ambala City (IN) for international business machines corporation, David Jason Hunt of Kirkwood MO (US) for international business machines corporation
IPC Code(s): H04W28/08, H04W28/10
Abstract: a computer-implemented method for addressing conflicts in a radio access network (ran) includes generating, by a non-real-time ran intelligent controller (non-rt ric), a policy for a near-real-time ran intelligent controller (near-rt ric) by analyzing an activity log of several xapps, which are being executed by the near-rt ric. the method further includes sending, by the non-rt ric the policy to the near-rt ric to cause the near-rt ric, in response to receiving a request from an xapp from the several xapps to update a parameter of the ran. the policy specifies an update the parameter based on the policy allowing the xapp to update the parameter. the policy further specifies maintaining the parameter unchanged based on the policy restricting the xapp to update the parameter.
Inventor(s): Shailendra Moyal of Pune (IN) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Akash U. Dhoot of Pune (IN) for international business machines corporation
IPC Code(s): H04W36/30, G06Q20/32, H04W36/14, H04W36/24
Abstract: a method for parallel connection for device transactions includes stablishing a first connection to perform a transaction by a client device. the method also includes identifying a plurality of available connections supported by the client device to perform the transaction. the method also includes initializing the plurality of available connections to perform the transaction, wherein each available connection represents a parallel connection to the first connection. the method also includes identifying at least one potential connectivity issue with the first connection based on a comparison between historical network data for the first connection and current network data for the first connection. the method also includes performing a handoff of the transaction between the first connection and a second connection from the plurality of available connections.
Inventor(s): Matthew Doyle of Chatfield MN (US) for international business machines corporation, DAVID CLIFFORD LONG of WAPPINGERS FALLS NY (US) for international business machines corporation, Matteo Cocchini of New York NY (US) for international business machines corporation, Russell A. Budd of North Salem NY (US) for international business machines corporation, James Busby of New Paltz NY (US) for international business machines corporation, Roger S. Krabbenhoft of Rochester MN (US) for international business machines corporation, Arthur J. Higby of Cottekill NY (US) for international business machines corporation
IPC Code(s): H05K1/02, H01P3/08, H01P11/00
Abstract: an electronic component includes a first trace configured to transmit a first signal and a second trace configured to transmit a second signal. the electronic component further includes a layer of conductive material separated from the first and second traces by a layer of insulative material. the electronic component further includes a first vertical wall formed in direct contact with the layer of conductive material. the electronic component further includes a second vertical wall formed in direct contact with the layer of conductive material. the second vertical wall is separated from the first vertical wall by a void, and the void extends between the first trace and the second trace.
Inventor(s): MARK D. SCHULTZ of OSSINING NY (US) for international business machines corporation
IPC Code(s): H05K7/20, F28F13/08
Abstract: a compliant counter-flow cold plate for component cooling includes a manifold body configured to be thermally coupled to a heat generating component and configured to be compliant under a distributed pressure load, and a plurality of expanding channels within the manifold body. at least one of the plurality of expanding channels extends from an inlet portion of the manifold body to an outlet portion of the manifold body.
Inventor(s): Nicholas A. Masluk of Putnam Valley NY (US) for international business machines corporation
IPC Code(s): H05K7/20, G06N10/40
Abstract: a thermal radiation shield interface for cryogenic systems includes a first element with a distal, free end. flanges project from the distal, free end of the first element. a second element also includes a distal, free end. flanges project from the distal, free end of the second element. the flanges of the first element and the flanges of the second element are positioned in an interleaved arrangement to cover an opening between the first element and the second element shielding the opening from radiation leakage.
Inventor(s): Min Gyu Sung of Latham NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Heng Wu of Santa Clara CA (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation
IPC Code(s): H01L27/11
Abstract: an integrated circuit structure includes a memory cell and multiple transistors therein. the multiple transistors are formed using channels including a stack having alternating layers of conductive semiconductor material and layers of other material that are insulative. two or more of the multiple transistors have a same number of layers of the conductive semiconductor material in corresponding channel regions but have different numbers of active layers and inactive layers of the conductive semiconductor material. an active layer is a layer forming a channel in the channel region that is electrically coupled to s/d regions in a corresponding transistor, while a floating layer is a layer in the channel region electrically isolated from the s/d regions in the corresponding transistor. methods for forming the integrated circuit structure are disclosed.
Inventor(s): Min Gyu Sung of Latham NY (US) for international business machines corporation, Soon-Cheon Seo of Glenmont NY (US) for international business machines corporation, Chen Zhang of Guilderland NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Heng Wu of Santa Clara CA (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation
IPC Code(s): H01L27/11573, H01L27/11529
Abstract: the present invention provides semiconductor structures. the semiconductor structures may include a peripheral complimentary metal-oxide semiconductor (cmos) substrate, a first vertical nand cell on a first side of the cmos substrate, and a second vertical nand cell on a second side of the cmos substrate opposite the first side.
Inventor(s): Wu-Chang Tsai of Albany NY (US) for international business machines corporation, Ailian Zhao of Slingerlands NY (US) for international business machines corporation, Ashim Dutta of Clifton Park NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L27/105, H01L23/48
Abstract: a semiconductor structure is presented including a first memory array and a second memory array directly connected to the first memory array by nanosheet stacks and backside contacts. the first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (cmos) wafer. the nanosheet stacks separate the first memory array from the second memory array so that two different types of memory devices are integrated together into a single cmos chip.
Inventor(s): Hsueh-Chung Chen of Cohoes NY (US) for international business machines corporation, Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Yann Mignot of Slingerlands NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L43/12, G11C11/16, H01L27/22, H01L43/02, H01L43/08
Abstract: a semiconductor device is provided. the semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (mtj) stack on the bottom electrode, and an upper electrode on the mtj stack. the semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.
Inventor(s): Luxherta Buzi of Chappaqua NY (US) for international business machines corporation, Robert L. Bruce of White Plains NY (US) for international business machines corporation, John M. Papalia of New York NY (US) for international business machines corporation, Lynne Marie Gignac of Beacon NY (US) for international business machines corporation
IPC Code(s): H01L45/00, H01L27/24
Abstract: techniques for sidewall passivation and removal of redeposited materials and processing damage from phase change memory materials are provided. in one aspect, a phase change memory device includes: one or more phase change memory cells, where each of the phase change memory cells includes a phase change material between a bottom electrode and a top electrode; and a carbon and oxygen-containing passivation layer on sidewalls of the phase change material. an ovonic threshold switch can also be present between the bottom and top electrodes, in series with the phase change material, and the carbon and oxygen-containing passivation layer can also be present on sidewalls of the ovonic threshold switch. a method of fabricating the present phase change memory devices is also provided.
Inventor(s): Luxherta Buzi of Chappaqua NY (US) for international business machines corporation, ROBERT L. BRUCE of White Plains NY (US) for international business machines corporation, Charlie Tabachnick of Astoria NY (US) for international business machines corporation, Marinus Johannes Petrus Hopstaken of Carmel NY (US) for international business machines corporation
IPC Code(s): H01L45/00, H01L27/24
Abstract: techniques for improving switching properties of phase change memory devices by boron surface passivation of the phase change memory material are provided. in one aspect, a phase change memory device includes: one or more phase change memory cells, each having a phase change material between a bottom electrode and a top electrode; and a boron-containing and nitrogen-containing bilayer on sidewalls of the phase change material to protect the phase change material from exposure to oxygen. an ovonic threshold switch can be implemented between the bottom electrode and the top electrode, in series with the phase change material. a method of fabricating the present phase change memory devices is also provided.
International Business Machines Corporation patent applications on March 21st, 2024
- International Business Machines Corporation
- A63F13/798
- A63F13/46
- H04L9/00
- International business machines corporation
- B60W30/09
- B60W30/095
- G06V20/58
- B60W40/09
- G01C21/34
- G06Q50/30
- G06F3/01
- G16H40/63
- G06F3/04895
- G10L15/22
- G06F3/06
- G06F8/35
- G06F9/54
- G06F8/41
- G06F8/36
- G06F9/455
- G06F9/38
- G06F8/61
- G06N20/00
- G06F9/50
- G06F11/07
- G06F21/55
- G06F11/36
- G06F12/121
- G06F16/23
- G06F16/33
- G06F40/205
- G06F40/263
- G06F16/35
- G06F16/31
- G06F16/332
- G06F40/30
- G06F16/9535
- G06F21/31
- G06F21/56
- G06F21/51
- G06F21/62
- G06F16/21
- G06N5/02
- G06F30/398
- G06F40/20
- G06F40/35
- G06F40/166
- G06F40/279
- G06F40/40
- G06F40/47
- G06F40/49
- G06F40/58
- G06N3/08
- G06N3/04
- G06N10/40
- H01L27/18
- H01L39/04
- H01L39/06
- H01L39/12
- G06Q10/06
- G06F11/32
- G06Q10/0875
- G06Q30/0601
- G06Q20/38
- G06Q20/40
- G06Q30/06
- G06Q30/02
- G06T17/00
- G06T5/00
- G06T19/20
- G06T19/00
- G06K7/10
- G06T15/20
- G06V10/74
- G06V40/20
- G06V10/22
- G06T11/20
- G06V10/82
- G06V20/20
- G06V10/764
- G06V10/774
- G06V10/10
- G06V10/26
- G06V20/70
- G06V30/148
- G06V30/182
- G06V30/412
- G06F3/0482
- G06F40/237
- G06V30/416
- G08B21/10
- G16Y20/10
- G08G1/005
- G08G1/16
- G09B5/06
- G06F3/0354
- G09B19/00
- G09B5/02
- G10L21/0272
- G10L15/26
- G10L25/78
- G11B27/031
- H01L21/768
- H01L23/522
- H01L21/8234
- H01L23/528
- H01L23/48
- H01L29/06
- H01L29/08
- H01L29/66
- H01L29/775
- H01L23/00
- H01L25/065
- H01L21/02
- H01L21/306
- H01L29/78
- H01L27/02
- H01L27/092
- H01L21/8238
- H01L29/423
- H01L21/321
- H01L21/822
- H01L29/40
- H01L29/417
- H01L29/786
- H01L29/20
- H01L27/06
- H01L29/861
- H01L27/088
- H01L29/16
- H01L29/161
- H01M50/583
- H05K1/11
- H01R12/72
- H02J50/90
- H02J50/80
- H03F19/00
- H04B7/08
- H04B1/30
- H04B7/06
- H04L7/00
- H04L25/24
- H04L51/224
- H04L12/18
- H04L51/216
- H04L9/40
- G06F9/451
- H04L65/401
- H04W12/02
- H04W12/08
- H04W16/04
- H04W8/00
- H04W28/08
- H04W28/02
- H04W28/10
- H04W36/30
- G06Q20/32
- H04W36/14
- H04W36/24
- H05K1/02
- H01P3/08
- H01P11/00
- H05K7/20
- F28F13/08
- H01L27/11
- H01L27/11573
- H01L27/11529
- H01L27/105
- H01L43/12
- G11C11/16
- H01L27/22
- H01L43/02
- H01L43/08
- H01L45/00
- H01L27/24
- H01L29/0673
