International Business Machines Corporation patent applications on April 4th, 2024
Patent Applications by International Business Machines Corporation on April 4th, 2024
International Business Machines Corporation: 64 patent applications
International Business Machines Corporation has applied for patents in the areas of H01L29/775 (16), H01L29/06 (11), H01L29/0673 (10), H01L23/528 (9), H01L29/66 (9)
With keywords such as: region, computer, data, semiconductor, portion, based, source, layer, drain, and device in patent application abstracts.
Patent Applications by International Business Machines Corporation
Inventor(s): Tushar Agrawal of West Fargo ND (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation
IPC Code(s): G05D1/10, B64C39/02, G06Q10/08
Abstract: managing a package delivery system deploying an unmanned vehicle including an inflatable unit for reducing package vibration in a transportation vehicle. package data is received at a computer, and the package data includes package descriptions. spatial positioning of the packages in the transport space is tracked to determine, spatial positioning changes between the packages in the transport space based on the package data received at the computer and the transport. one or more unmanned vehicles are delivered to the transport space based on the spatial positioning changes in the transport space, and the unmanned vehicles including inflatable units. the inflatable units are deployed in the transport space by inflating the inflatable units at locations in the transport space based on the spatial positioning changes to discourage package movement in the transport space.
Inventor(s): Beth Ann Peterson of Tucson AZ (US) for international business machines corporation, Matthew Richard Craig of Sahuarita AZ (US) for international business machines corporation, John G. Thompson of Tucson AZ (US) for international business machines corporation, John R. Paveza of Morgan Hill CA (US) for international business machines corporation, Nicolas Marc Clayton of Warrington (GB) for international business machines corporation, Terry O'Connor of High Peak (GB) for international business machines corporation, David Michael Shackelford of Tucson AZ (US) for international business machines corporation
IPC Code(s): G06F3/06
Abstract: a computer-implemented method for effectively delivering notifications in data storage environments includes, receiving, by a storage controller from a host system, a request to register the host system with the storage controller to receive notifications. these notifications may be associated with a selected type of event detected by the storage controller. in certain embodiments, the selected type of event is a space-related condition associated with a particular storage resource controlled by the storage controller. the computer-implemented method registers the host system with the storage controller. in response to detecting an event of the selected type on the storage controller, the computer-implemented method transmits a notification from the storage controller to the host system to provide notice of the event. a corresponding system and computer program product are also disclosed.
Inventor(s): Guang Han Sui of Beijing (CN) for international business machines corporation, Jin Chi He of XIAN (CN) for international business machines corporation, Peng Hui Jiang of Beijing (CN) for international business machines corporation, Jun Su of Beijing (CN) for international business machines corporation, Gang Tang of Nanjing (CN) for international business machines corporation
IPC Code(s): G06F8/65, G06F9/48
Abstract: a computer implemented method, apparatus, system, and computer program product manages updates to images. a computer system determines shared layers present between the images selected for update management. the images comprise executable code that are run to create containers. the computer system detects a change in a shared layer in the shared layers for an image in the images. the computer system updates the shared layer in the shared layers in a set of the images having the shared layer in response to detecting the change to the shared layer for the image. according to other illustrative embodiments, a computer system and a computer program product for managing updates to images are provided.
Inventor(s): Madhu Pavan Kothapally of Warangal (IN) for international business machines corporation, Rajesh Kumar Pirati of Guntur (IN) for international business machines corporation, Bharath Sakthivel of Theni (IN) for international business machines corporation, Sarika Sinha of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F9/4401, G06F1/3212
Abstract: tasks are selected for hibernation by recording user preferences for tasks having no penalty for hibernation and sleep; and assigning thresholds for battery power at which tasks are selected for a least one of hibernation and sleep. the assigning of the thresholds for battery power include considering current usage of hardware resources by a user and battery health per battery segment. a penalty score is determined for tasks based upon the user preferences for tasks having no penalty, and task performance including at least one of frequency of utilization, memory utilization, task dependency characteristics and task memory hierarchy. the penalty performance is a value including both the user preference and the task performance. tasks can then be put into at least one of hibernation mode and sleep mode dictated by their penalty performance during the thresholds for battery power.
Inventor(s): Heng Wang of Changping District (CN) for international business machines corporation, Xiao Ling Chen of Changping District (CN) for international business machines corporation, Xin Peng Liu of Austin TX (US) for international business machines corporation, Tao Guan of Toronto (CA) for international business machines corporation, Wei Wu of Beijing (CN) for international business machines corporation
IPC Code(s): G06F9/445
Abstract: a computer-implemented process is disclosed. an application is loaded into a local address space. a request by the application to load a target shared library is intercepted by an interceptor. using the interceptor and based upon the request being intercepted, a shared library correlation table is searched for a loading count and a loading policy associated with the target shared library. based upon the loading count and the loading policy, a selection is made between loading the target shared library as a shared library container, and loading the target shared library into the local address space. the target shared library is loaded based upon the selecting. the loading count represents a number of times the target shared library was loaded, and the loading policy indicates how the target shared library is to be loaded.
Inventor(s): Vijay Sundaresan of Markham (CA) for international business machines corporation
IPC Code(s): G06F9/455, G06F9/30, G06F11/36
Abstract: the present specification describes a computer-implemented method. a first comparison test is executed to determine whether an unknown object is of a first sub-class of a class of objects. responsive to determining that the unknown object is not of the first sub-class, it is determined whether the unknown object is an instance of a second sub-class by determining whether there are additional sub-classes other than the first sub-class and a second sub-class. responsive to determining that there are additional sub-classes, the second code fragment executes while refraining from assuming the unknown object is of a particular sub-class.
Inventor(s): Jonathan Lenchner of YORKTOWN HEIGHTS NY (US) for international business machines corporation, Lior Horesh of YORKTOWN HEIGHTS NY (US) for international business machines corporation, Francesca Rossi of Yorktown Heights NY (US) for international business machines corporation
IPC Code(s): G06F9/50, G06F8/36
Abstract: an example operation may include one or more of invoking, via an operating system, execution of a plurality of software programs having a first mode of operation that causes the plurality of software programs to operate in a first resource consuming mode, monitoring physical resources of a computing device that are consumed by the plurality of software programs, determining to reduce or allow expanded consumption of the physical resources of the computing device by the plurality of software programs based on the monitored physical resources, and in response to the determination, switching from a first mode of operation of a software program from among the plurality of software programs and to a second mode of operation of the software program that causes the software program to operate in a second resource consuming mode that consumes either less or more physical resources than the first resource consuming mode.
Inventor(s): Jing Jing Wei of Beijing (CN) for international business machines corporation, Yue Wang of Beijing (CN) for international business machines corporation, Shu Jun Tang of Beijing (CN) for international business machines corporation, Yang Kang of Beijing (CN) for international business machines corporation, Yi Fan Wu of Beijing (CN) for international business machines corporation, Qi Han Zheng of Beijing (CN) for international business machines corporation, Jia Lin Wang of Beijing (CN) for international business machines corporation
IPC Code(s): G06F9/50
Abstract: intelligent process management is provided. a start time is determined for an additional process to be run on a worker node within a duration of a sleep state of a task of a process already running on the worker node by adding a first defined buffer time to a determined start time of the sleep state of the task. a backfill time is determined for the additional process by subtracting a second defined buffer time from a determined end time of the sleep state of the task. a scheduling plan is generated for the additional process based on the start time and the backfill time corresponding to the additional process. the scheduling plan is executed to run the additional process on the worker node according to the start time and the backfill time corresponding to the additional process.
Inventor(s): Guang Han Sui of Beijing (CN) for international business machines corporation, Wei Ge of Beijing (CN) for international business machines corporation, Lan Zhe Liu of BEIJING (CN) for international business machines corporation, Guo Liang Wang of BEIJING (CN) for international business machines corporation
IPC Code(s): G06F9/50
Abstract: a present invention embodiment requests resources for a set of tasks from different resource providers. the set of tasks includes first tasks and second tasks of longer duration than the first tasks. the resources are revocable by the different resource providers based on processing demand. performance of the first tasks is initiated on the resources, and stable resources are identified based on revocation of the resources during performance of the first tasks. performance of the second tasks are initiated on the identified stable resources. requests for the resources to the different resource providers are adjusted based on resource provider information collected in response to completion of the set of tasks.
Inventor(s): Madhana Sunder of Meridian ID (US) for international business machines corporation, Christopher Muzzy of Burlington VT (US) for international business machines corporation, James Mansfield Crafts of Warren VT (US) for international business machines corporation, Noah Singer of White Plains NY (US) for international business machines corporation
IPC Code(s): G06F11/20, G06F11/07, G06F11/30
Abstract: an approach for managing and minimized failure of one or more devices in a computerized cluster and/or vehicle infrastructure is disclosed. the proactive approach for mitigating such black swan events as it relate to hardware failures (e.g., servers, network, vehicle systems/architecture, etc.). the approach would proactively inactivate “suspect” components (i.e., components that are completely functional in multiple systems) based on component vintage data from systems where components have failed or malfunctioned. a dedicated service is actively updating suspect components and their respective vintages spread across various systems. furthermore, the approach backups components using different vintages are effectively utilized to avoid complete system failure.
Inventor(s): Tohru Hasegawa of Tokyo (JP) for international business machines corporation, Hiroshi Itagaki of Yokohama-shi (JP) for international business machines corporation, Tsuyoshi Miyamura of Yokohama-shi (JP) for international business machines corporation, Atsushi Abe of Ebina (JP) for international business machines corporation, Noriko Yamamoto of Tokyo (JP) for international business machines corporation, Shinsuke Mitsuma of Machida-shi (JP) for international business machines corporation
IPC Code(s): G06F16/16, G06F16/13, G06F16/172
Abstract: an approach for deleting a file from a primary file system. the approach deletes a directory entry, associated with a file, from an in-memory index associated with a secondary file system. the approach updates an index cache associated with a secondary file system, based on the in-memory index. the approach updates a dirty flag, associated with the secondary file system, to a value of true.
Inventor(s): Shuo Li of Beijing (CN) for international business machines corporation, Xiaobo Wang of Beijing (CN) for international business machines corporation, Sheng Yan Sun of Beijing (CN) for international business machines corporation, YING ZHANG of Beijing (CN) for international business machines corporation
IPC Code(s): G06F16/2455, G06F11/34, G06F16/22
Abstract: computer technology for retrieving data stored in a table that includes the following computer operations: receiving, from persistent storage of a computer, an original index tree data structure; storing, in volatile memory, a memory-based index tree data structure based on the original index tree data structure, with the memory-based index tree data structure including: a root node, a set of hierarchically arranged intermediate layer(s) with each intermediate layer including a plurality of non-leaf nodes, and a leaf layer including a plurality of leaf nodes; and retrieving data from a table in a database, with the retrieval including traversing the memory-based index tree data structure through a plurality of child lock pointers to locate pages including the data to be retrieved from the table.
Inventor(s): Andrea Giovannini of Zurich (CH) for international business machines corporation, Joy Tzung-yu Wu of San Jose CA (US) for international business machines corporation, Tanveer Syeda-Mahmood of Cupertino CA (US) for international business machines corporation, Ashutosh Jadhav of San Jose CA (US) for international business machines corporation
IPC Code(s): G06F16/2458, G06F16/248, G06F16/901, G16H10/60
Abstract: mechanisms are provided to implement a visual analytics pipeline. the mechanisms generate, from an input database of records, a chronology-aware graph data structure of a plurality of records based features specified in an ontology data structure. the chronology-aware graph data structure has vertices representing one or more of events or records based features corresponding to events, and edges representing chronological relationships between events. the mechanisms execute a chronology-aware graph query on the chronology-aware graph data structure to generate a filtered set of vertices and corresponding features corresponding to criteria of the chronology-aware graph query. the mechanisms execute a pattern discovery operation on the filtered set of vertices and corresponding features to identify a subset of vertices and corresponding features that correspond to a relatively higher frequency set of patterns of event paths, and generate a visual analytics graphical representation for the subset of vertices and corresponding features.
Inventor(s): Richard Obinna Osuala of Munich (DE) for international business machines corporation, Dominik Moritz Stein of Oberding (DE) for international business machines corporation, Andrea Giovannini of Zurich (CH) for international business machines corporation
IPC Code(s): G06F16/332, G06F16/33, G06F40/284
Abstract: in several aspects for querying a data source represented by data object embeddings in a vector space, a processor inputs, to a trained embedding generation model, a received query and at least one token for receiving from the trained embedding generation model a set of embeddings of the vector space. the set of embeddings comprises an embedding of the received query and at least one embedding of the at least one token respectively, wherein the embedding of each token is a prediction of an embedding of a supplement of the query. the data object embeddings may be searched for data object embeddings that match the set of embeddings. this may result in search result embeddings of the set of embeddings. data objects that are represented by the search result embeddings may be determined. at least part of the determined data objects may be provided.
Inventor(s): Meghan McGrath of Highland NY (US) for international business machines corporation, Jonathan Fry of Fishkill NY (US) for international business machines corporation, MICHAEL KANE of Poughkeepsie NY (US) for international business machines corporation, James Cox of Lagrangeville NY (US) for international business machines corporation, Ximena Bates-Forero of Schererville IN (US) for international business machines corporation
IPC Code(s): G06F21/62
Abstract: a method, an apparatus, a system, and a computer program product for processing messages. a computer system parses a message to identify key value pairs for confidential information in the message. the computer system creates a redacted message in which values in the key value pairs identified for the confidential information are replaced with plaintext tags. the computer system stores the key value pairs in a secure database. the computer system stores the redacted message in a plaintext database.
Inventor(s): Thomas Kalla of Boeblingen (DE) for international business machines corporation, Jentje Leenstra of Bondorf (DE) for international business machines corporation, Richard Louis Henry Carbone of Webster NY (US) for international business machines corporation, Philipp Salz of Altdorf (DE) for international business machines corporation
IPC Code(s): G06F3/06
Abstract: a computer implemented method for automated generation and verification of a technology specific logic model and a technology independent logic model of a memory array, the method at least comprising: having a first set of parameters; having a set of constraints, creating a second set of parameters; generating the technology independent model of the memory array wherein the second set of parameters and the set of constraints are used; generating the technology specific model of the memory array wherein the first set of parameters and the set of constraints are used; verifying the technology independent model and the technology specific model for equivalence on a sequential logic basis.
Inventor(s): Zhenfang Chen of Cambridge MA (US) for international business machines corporation, Chuang Gan of Cambridge MA (US) for international business machines corporation, Bo Wu of Cambridge MA (US) for international business machines corporation, Dakuo Wang of Cambridge MA (US) for international business machines corporation
IPC Code(s): G06F40/205, G06N3/04, G06T7/12
Abstract: a computer-implemented method for fine-grained referring expression comprehension is provided. the computer-implemented method includes receiving, at a processor, a textual expression and an image as inputs and executing, at the processor, fine-grained referring expression comprehension. the executing includes decomposing the textual expression into different textual modules, extracting visual regional proposals from the image, using language-guided graph neural networks to mine fine-grained object relations from the visual regional proposals and aggregating different matching similarities between the different textual modules and the fine-grained object relations.
Inventor(s): KENTA WATANABE of Soka-shi (JP) for international business machines corporation, Takahito Tashiro of Mitaka-shi (JP) for international business machines corporation, Takashi Fukuda of TOKYO (JP) for international business machines corporation, TAIHEI MIYAMOTO of Nakano (JP) for international business machines corporation
IPC Code(s): G06F40/268, G06F16/35, G06F40/49
Abstract: in an approach for generating a user-specific personal corpus, a processor creates a basic corpus for a first user using a first set of data sources, wherein the basic corpus includes one or more basic words and one or more vectors of the one or more basic words. a processor extracts a set of text from a second set of data sources associated with the first user. responsive to finding an unknown word included in the set of text extracted, a processor updates the basic corpus, wherein the basic corpus is updated by replacing a vector of the unknown word with an average vector of the one or more basic words in the basic corpus created and registering the unknown word in a first personal corpus.
Inventor(s): Jin Shi of Ningbo (CN) for international business machines corporation, Wen Juan Nie of Ningbo (CN) for international business machines corporation, Jing Lei Guo of Ningbo (CN) for international business machines corporation, Lu Fu of Ningbo (CN) for international business machines corporation, Ke Huan Yin of Ningbo (CN) for international business machines corporation, Jie Jiang of Ningbo (CN) for international business machines corporation
IPC Code(s): G06F40/40, G06F40/20, G06F40/30, G06T11/20
Abstract: techniques are described with respect to a system, method, and computer product for visualizing viewpoints. an associated method includes receiving access to a multi-party discussion occurring via a telecommunication system and analyzing the multi-party discussion using natural language processing. the method further includes extracting a plurality of viewpoints of the multi-party discussion based on the analysis, synthesizing a subset of the plurality of viewpoints based on the content of each viewpoint of the plurality of viewpoints, and transmitting a rendered synthesized visualization of the subset.
Inventor(s): Michael Robert Glass of New York NY (US) for international business machines corporation, Gaetano Rossiello of New York NY (US) for international business machines corporation, Md Faisal Mahbub Chowdhury of New York NY (US) for international business machines corporation, Alfio Massimiliano Gliozzo of New York NY (US) for international business machines corporation
IPC Code(s): G06F40/56, G06N5/02, G06N5/04
Abstract: methods, systems, and computer program products for natural language data generation using automated knowledge distillation techniques are provided herein. a computer-implemented method includes retrieving, in response to an input query, a set of passages from at least one knowledge base by processing the input query using a first set of artificial intelligence techniques; ranking at least a portion of the set of passages by processing the set of passages using a second set of artificial intelligence techniques; generating at least one natural language answer, in response to the input query, by processing a subset of the set of passages in connection with automated knowledge distillation techniques based on the ranking of the at least a portion of the set of passages; and performing automated actions based on the ranking of the at least a portion of the set of passages and/or the at least one generated natural language answer.
Inventor(s): Manish Anand Bhide of Hyderabad (IN) for international business machines corporation, Prateek Goyal of Indore (IN) for international business machines corporation
IPC Code(s): G06N3/04, G06N3/08
Abstract: one or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to predicting bias in an artificial intelligence (ai) model. a system can comprise a memory configured to store computer executable components; and a processor configured to execute the computer executable components stored in the memory, wherein the computer executable components can comprise a data generation component that can generate a set of structured test data to test likelihood of an ai model generating biased outputs, based on analysis of payload logging data; and an alerting component that can alert a user of likelihood that the ai model will generate the biased outputs, wherein the alerting component can generate an alert in response to at least a first set of records approaching a defined threshold.
Inventor(s): Vivekananda P. Adiga of Ossining NY (US) for international business machines corporation, Russell A. Budd of North Salem NY (US) for international business machines corporation, Charles Thomas Rettner of San Jose CA (US) for international business machines corporation, Stephen M. Gates of New York NY (US) for international business machines corporation
IPC Code(s): G06N10/40, H01L21/822, H01L23/525, H03K17/92
Abstract: a method of constructing a superconducting switch includes providing a substrate. a first superconducting metal line is fabricated on the substrate, wherein the superconducting metal line has a left portion, a right portion, and a center portion patterned along a first crystalline direction of the substrate. one or more etch release holes are provided in the center portion of the first superconducting metal line. the center portion of the superconducting metal line is released from the substrate with an anisotropic etch through the etch release holes in a manner that reduces the undercut distance elsewhere on the substrate
Inventor(s): Amadou Ba of Navan (IE) for international business machines corporation, Venkata Sitaramagiridharganesh Ganapavarapu of Elmsford NY (US) for international business machines corporation, Seshu Tirupathi of Dublin (IE) for international business machines corporation, Bradley Eck of Dublin (IE) for international business machines corporation
IPC Code(s): G06N20/00
Abstract: a computer-implemented method, a computer program product, and a computer system for retraining a model in case of a drift in machine learning. a computer detects a drift in machine learning. a computer identifies in a database features and a response of a machine learning model. a computer determines a time window of the drift. a computer extracts, from the database, data of the features and the response in the time window. a computer determines whether extracted data is sufficient for retraining the machine learning model. a computer, in response to determining that the extracted data is not sufficient for retraining the machine learning model, interpolates one or more of the features for a predetermined future time horizon. a computer interpolates a response corresponding to one or more interpolated features. a computer retrains the machine learning model, using the one or more interpolated features and an interpolated response corresponding thereto.
Inventor(s): Bryson Chisholm of Stevensville (CA) for international business machines corporation, Shikhar Kwatra of San Jose CA (US) for international business machines corporation, Shaikh Shahriar Quader of Oshawa (CA) for international business machines corporation, Ayesha Bhangu of Whitby (CA) for international business machines corporation, Jack Zhang of Unionville (CA) for international business machines corporation, Shabana Dhayananth of Brampton (CA) for international business machines corporation, Tarandeep kaur Randhawa of Stratford (CA) for international business machines corporation
IPC Code(s): G06N20/00, G06F16/33
Abstract: an embodiment of the present invention extracts information from a natural language query requesting performance of a task. a machine learning model determines a task that corresponds to the task requested by the natural language query based on the extracted information. a query is generated for retrieving data from a plurality of different data sources based on the extracted information. the data for the determined task is retrieved from the plurality of different data sources based on the generated query. the determined task is performed using the retrieved data. present invention embodiments include a method, system, and computer program product for processing a natural language query in substantially the same manner described above.
Inventor(s): Tushar Agrawal of West Fargo ND (US) for international business machines corporation, Martin G. Keen of Cary NC (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G06N20/00, B60W60/00
Abstract: embodiments of the present invention provide an approach for providing in-vehicle predicted context-based proactive driving training using an autonomous vehicle. a knowledge corpus is established from a driver's previous driving experience. a potential driving context (or scenario) is identified for a forthcoming driving route. an experience gap analysis is performed between the driver's experience and the potential driving context. if an experience gap exists, an in-vehicle mixed reality driving training simulation is provided in a selected location by the autonomous vehicle. the driver's responses to the training simulation can optionally be monitored and a determination can made based on the driver responses as to the suitability of the driver to safely address the potential driving context.
Inventor(s): Thai Quoc Tran of San Jose CA (US) for international business machines corporation, Cindy Han Lu of San Jose CA (US) for international business machines corporation, Megan Kostick of Edmonds WA (US) for international business machines corporation, Michael Brewer of Austin TX (US) for international business machines corporation
IPC Code(s): G06T11/60, G06F40/143, G06V20/20
Abstract: a computer-implemented method according to one embodiment includes performing object detection on a frame to identify a set of objects within the frame, and determining a location of each object of the set of objects within the frame. the method further includes constructing a code tree structure for the frame. the code tree structure defines the determined locations. a rule defining modifications to make to at least some of the objects is received and the code tree structure is crawled. the rule is applied to the objects during the crawling. the method further includes layering the modifications defined in the rule on the set of objects within the frame. a computer program product according to another embodiment includes a computer readable storage medium having program instructions embodied therewith. the program instructions are readable and/or executable by a computer to cause the computer to perform the foregoing method.
Inventor(s): Xiao Xia Mao of Shanghai (CN) for international business machines corporation, Meng Ran Chen of Shanghai (CN) for international business machines corporation, Ya Qing Chen of Shanghai (CN) for international business machines corporation, Yan An of Shanghai (CN) for international business machines corporation, Yin Hu of Ningbo (CN) for international business machines corporation
IPC Code(s): G06T19/00, G06F40/20, G06T5/00, G06T19/20, G06V10/74
Abstract: systems and methods enable machine learning (ml) feature prioritization to reduce image noise in a virtual environment. in embodiments, a method includes providing a device access to a virtual environment via a graphical user interface (gui), the environment including images of objects and a navigation tool enabling a user to navigate the environment and interact with the images; monitoring interaction data of the user; calculating priority values for predefined areas of a first object in the environment, using an ml model trained with historic user interaction data and object data; processing image data of one or more of the predefined areas of the first object using image processing to generate new data based on display specifications of the client device and the priority values; and pre-loading the new data in a buffer, such that the new data is available prior to display of the new data to the user.
Inventor(s): Fearghal O'Donncha of Aran Islands (IE) for international business machines corporation, Malvern Madondo of Atlanta GA (US) for international business machines corporation, Muneeza Azmat of East Lansing MI (US) for international business machines corporation, Michael Jacobs of Beacon NY (US) for international business machines corporation, Raya Horesh of North Salem NY (US) for international business machines corporation
IPC Code(s): G06V10/74, G06V10/46, G06V10/762, G06V10/82
Abstract: embodiments are directed to a computer-implemented method of analyzing a land region that has been decomposed into a plurality of regular or irregular sub-regions. the computer-implemented method includes applying, using a processor system, a feature extraction process that extracts a set of sub-region environmental descriptors for each of the plurality of sub-regions. the processor system applies a similarity analysis to the set of sub-region environmental descriptors to generate groups of the plurality of sub-regions. the processor system creates a plurality of group-based graphs by encoding each of the groups into a corresponding group-based graph. a spatio-temporal neural network is used to train a model based at least in part on the plurality of group-based graphs.
Inventor(s): Michele Merler of New York City NY (US) for international business machines corporation, Dhiraj Joshi of Edison NJ (US) for international business machines corporation, Apurv Gupta of Vadodara (IN) for international business machines corporation, Sebastien Gilbert of Granby (CA) for international business machines corporation, Shyama Prosad Chowdhury of West Bengal (IN) for international business machines corporation, Chidansh Amitkumar Bhatt of Hightstown NJ (US) for international business machines corporation, Nirmit V. Desai of Yorktown Heights NY (US) for international business machines corporation
IPC Code(s): G06V10/764, G06V10/22, G06V10/74, G06V10/84, G06V30/19
Abstract: automated analog gauge reading is provided. the method comprises a computer system receiving input of an image and detecting at least one analog gauge in the image. the computer system corrects the orientation of the analog gauge in the image and detects scene text and tick labels on the analog gauge. the computer system determines a position of a pointer on the analog gauge relative to the scene text and outputs a gauge reading value based on an arithmetic progression of tick labels and angle of the pointer with respect to minimum and maximum values on the analog gauge.
Inventor(s): Pouya Hashemi of Purchase NY (US) for international business machines corporation, Christopher SAFRANSKI of Yorktown Heights NY (US) for international business machines corporation
IPC Code(s): G11C11/16, H01L27/22, H01L43/02, H01L43/08, H01L43/12
Abstract: a magnetic random access memory (mram) apparatus includes a magnetic tunnel junction (mtj) stack; a spin-orbit-torque (sot) layer that underlies the mtj stack; and a dielectric pillar that underlies the sot layer and the mtj stack. the sot layer has a stepped profile.
Inventor(s): Chinami Marushima of Urayasu-city (JP) for international business machines corporation, Toyohiro Aoki of Yokohama (JP) for international business machines corporation, Takashi Hisada of Hachiouji-shi (JP) for international business machines corporation, Marc A. Bergendahl of Rensselaer NY (US) for international business machines corporation
IPC Code(s): H01L23/13, H01L21/56, H01L23/00, H01L23/538, H01L25/065
Abstract: a semiconductor device includes a substrate, which further includes a cavity and a trench extended from the cavity. the semiconductor includes a first chip and a second chip on the substrate, a bridge chip interconnecting between the first and second chips and residing in the cavity, and underfill material filling the cavity and the trench, and surrounding the bridge chip.
Inventor(s): Tao Li of Slingerlands NY (US) for international business machines corporation, Liqiao Qin of Albany NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Kisik Choi of Watervliet NY (US) for international business machines corporation
IPC Code(s): H01L23/48, H01L21/8234, H01L29/06, H01L29/417, H01L29/66, H01L29/775, H01L29/786
Abstract: a semiconductor device includes power rails formed in a backside of a wafer. a gate of a first transistor on the wafer is connected to a power rail through a via-to-backside power rail (vbpr) gate contact. a source/drain (s/d) region of a second transistor on the wafer is connected to a power rail through a vbpr s/d contact. the vbpr gate contact partially vertically overlaps a gate cut region between the first transistor and the second transistor.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Brent A. Anderson of Jericho VT (US) for international business machines corporation, Kisik Choi of Watervliet NY (US) for international business machines corporation, Su Chen Fan of Cohoes NY (US) for international business machines corporation, Shogo Mochizuki of Mechanicville NY (US) for international business machines corporation, SON NGUYEN of Schenectady NY (US) for international business machines corporation
IPC Code(s): H01L23/48, H01L21/8238, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
Abstract: a semiconductor device includes a nanostructure field effect transistor (fet). the fet includes a gate and a first source or drain (s/d) region. a frontside s/d contact may be connected to and extends vertically upward from a top surface of the first s/d region. the fet further includes a second s/d region. the second s/d region extends below a bottom surface of the gate. a backside s/d contact may be connected to and extend vertically downward from a bottom surface of the second s/d region.
Inventor(s): Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Alexander Reznicek of Troy NY (US) for international business machines corporation, Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation, Oscar van der Straten of Guilderland Center NY (US) for international business machines corporation
IPC Code(s): H01L23/48, H01L27/088, H01L29/06, H01L29/417, H01L29/775, H01L29/786
Abstract: a semiconductor device includes a transistor having a source/drain region and a contact disposed on the source/drain region. the semiconductor device further includes a via extending from the contact along a side of the source/drain region to a power element. the contact and the via each comprise a plurality of conductive materials.
Inventor(s): Huai Huang of Clifton Park NY (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Hosadurga Shobha of Niskayuna NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation
IPC Code(s): H01L23/522, H01L21/768, H01L23/528, H01L25/065, H01L27/088
Abstract: a semiconductor structure comprises a first portion of an interconnect line comprising a first conducting line segment and a second conducting line segment separated by an isolating layer, and a second portion of the interconnect line comprising a third conducting line segment vertically stacked over at least a portion of the first conducting line segment and at least a portion of the second conducting line segment.
Inventor(s): Vivekananda P. Adiga of Ossining NY (US) for international business machines corporation, Russell A. Budd of North Salem NY (US) for international business machines corporation, Charles Thomas Rettner of San Jose CA (US) for international business machines corporation, Stephen M. Gates of New York NY (US) for international business machines corporation
IPC Code(s): H01L23/525
Abstract: a method of constructing a superconducting switch includes depositing a thin sacrificial layer on top of a substrate. the sacrificial layer is patterned to remove portions of the sacrificial layer except at a first portion of the substrate. a superconducting metal layer is patterned on top of the substrate and on top of the sacrificial layer. the superconducting metal layer is patterned to form a superconducting metal line over the sacrificial layer. the patterned sacrificial layer is etched from under the superconducting metal line to release the metal line from the substrate.
Inventor(s): Oscar van der Straten of Guilderland Center NY (US) for international business machines corporation, Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Scott A. DeVries of Albany NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/532
Abstract: a wire interconnect, a wire interconnect structure, and a method to form wire interconnect structures with locally widened profiles. the wire interconnect may include a first portion of the wire interconnect with a first width. the wire interconnect may also include a second portion of the wire interconnect with a second width, where the second width is greater than the first width, and where the second portion of the wire interconnect is above the first portion of the wire interconnect. the wire interconnect may also include a third portion of the wire interconnect with a third width, where the third width is less than the second width, and where the third portion of the wire interconnect is above the second portion of the wire interconnect.
Inventor(s): Brent A. Anderson of Jericho VT (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Junli Wang of Slingerlands NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L29/417, H01L29/78
Abstract: a first vtfet is provided on a wafer. a second vtfet is adjacent to the first vtfet on the wafer. a backside power deliver network is on a backside of the wafer. a shared frontside contact is on a frontside of the wafer. the shared frontside contact is connected to a first top source/drain region of the first vtfet, a second top source/drain region of the second vtfet, and the backside power delivery network.
Inventor(s): Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Nicolas Jean Loubet of Guilderland NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L21/768, H01L21/8234, H01L29/786
Abstract: a semiconductor device includes a backside power line located under a p-channel field effect transistor region and an n-channel field effect transistor region; a backside signal line located between the p-channel field effect transistor region and the n-channel field effect transistor region; and an airgap between the backside power line and the backside signal line.
Inventor(s): Ching-Tzu Chen of Ossining NY (US) for international business machines corporation, Christian Lavoie of Pleasantville NY (US) for international business machines corporation, Guy M. Cohen of Westchester NY (US) for international business machines corporation, Utkarsh Bajpai of Delmar NY (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Teodor Krassimirov Todorov of Yorktown Heights NY (US) for international business machines corporation, Oki GUNAWAN of Westwood NJ (US) for international business machines corporation, NATHAN P. MARCHACK of New York NY (US) for international business machines corporation, Peter Kerns of Sandy Hook CT (US) for international business machines corporation
IPC Code(s): H01L23/532, H01L21/768
Abstract: an interconnect structure including conducting layers of topological semi-metals and/or topological insulators. to increase charge carrier density in the conducting layers, a charge carrier doping layer present on at least one surface of the one or more conductive layers of topological semi-metals. the charge carrying doping layers have a charge carrier density greater than the topological semi-metals and/or topological insulators of the one or more conductive layers.
Inventor(s): Nicholas Alexander Polomoff of Hopewell Junction NY (US) for international business machines corporation, Eric Perfecto of North Salem NY (US) for international business machines corporation, Katsuyuki Sakuma of Fishkill NY (US) for international business machines corporation, Mukta Ghate Farooq of Hopewell Junction NY (US) for international business machines corporation, Spyridon Skordas of Troy NY (US) for international business machines corporation, Sathyanarayanan Raghavan of Ballston Lake NY (US) for international business machines corporation, Michael P. Belyansky of Halfmoon NY (US) for international business machines corporation
IPC Code(s): H01L23/00, H01L25/065
Abstract: a hybrid bonded semiconductor structure includes a first substrate and a second substrate each having an interface joined in a hybrid bond. each substrate has a die portion and a crackstop structure adjacent the die portion. one or more voids in the first substrate and the second substrate are formed in or about a portion of a periphery of each crackstop structure. at least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form a unified void with airgaps across the hybrid bond interface.
Inventor(s): Frank Robert Libsch of White Plains NY (US) for international business machines corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/544
Abstract: techniques are provided for intra-bonding multiple semiconductor integrated circuit chips to form multi-chip package structures. for example, a device comprises a first semiconductor die and a second semiconductor die. the first semiconductor die comprises a first overlap region which comprises a first array of metallic contacts. the second semiconductor die comprises a second overlap region which comprises a second array of metallic contacts. the first overlap region and the second overlap region are overlapped and bonded together with the first array of metallic contacts aligned to the second array of metallic contacts, and with the first semiconductor die and the second semiconductor die disposed laterally adjacent to each other.
Inventor(s): Min Gyu Sung of Latham NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Kangguo Cheng of Schenectady NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation
IPC Code(s): H01L27/092, H01L21/02, H01L21/822, H01L21/8238, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775
Abstract: embodiments of the present invention are directed to stacked field effect transistors (sfets) having integrated vertical inverters. in a non-limiting embodiment, a first nanosheet is vertically stacked over a second nanosheet. a common gate is formed around a channel region of the first and second nanosheets. a top source or drain region is formed in direct contact with the first nanosheet and a bottom source or drain region is formed in direct contact with the second nanosheet. a first portion of the top source or drain region is shorted to a first portion of the bottom source or drain region to define a common source or drain region. a second portion of the top source or drain region is electrically coupled to a second portion of the bottom source or drain region in series through the first nanosheet, the common source or drain region, and the second nanosheet.
Inventor(s): Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Kangguo Cheng of Schenectady NY (US) for international business machines corporation
IPC Code(s): H01L27/12, H01L21/762, H01L21/768, H01L21/8234, H01L21/84, H01L23/528
Abstract: a semiconductor chip device includes a substrate with a back end of line layer and a backside power delivery network. an input power line is electrically coupled to the backside power delivery network. dummy transistors are positioned in a circuit with analog or digital circuit elements. a power gating transistor is positioned in the circuit between the dummy transistors and the analog or digital circuit elements. power from the power input line is provided from the backside power delivery network, through the dummy transistors, and controlled by the power gating transistor for transfer to the analog or digital circuit elements. the device uses a backside delivery of power to the area of the dummy transistors to transfer power into the analog or digital circuit elements, which leaves more of the front side footprint for functional devices.
Inventor(s): Jingyun Zhang of Albany NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Ruqiang Bao of Niskayuna NY (US) for international business machines corporation, Prabudhya Roy Chowdhury of Albany NY (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L21/8238, H01L29/66, H01L29/775, H01L29/786
Abstract: embodiments of the present invention are directed to monolithic stacked field effect transistor (sfet) processing methods and resulting structures having dual middle dielectric isolation (mdi) separation. in a non-limiting embodiment of the invention, a first nanosheet is formed and a second nanosheet is vertically stacked over the first nanosheet. a gate is formed around a channel region of the first nanosheet and a channel region of the second nanosheet and a middle dielectric isolation structure is formed between the first nanosheet and the second nanosheet. the middle dielectric isolation structure includes a first middle dielectric isolation layer and a second middle dielectric isolation layer vertically stacked over the first middle dielectric isolation layer. a portion of the gate extends between the first middle dielectric isolation layer and the second middle dielectric isolation layer in the middle dielectric isolation structure.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Brent A. Anderson of Jericho VT (US) for international business machines corporation, Kisik Choi of Watervliet NY (US) for international business machines corporation, Su Chen Fan of Cohoes NY (US) for international business machines corporation, Shogo Mochizuki of Mechanicville NY (US) for international business machines corporation, SON NGUYEN of Schenectady NY (US) for international business machines corporation
IPC Code(s): H01L29/417, H01L23/528, H01L29/06, H01L29/40, H01L29/66, H01L29/775
Abstract: a semiconductor device includes a field effect transistor (fet). the fet includes a gate and a first source or drain (s/d) region. a frontside s/d contact may be connected to and extend vertically upward from a top surface of the first s/d region. the fet further includes a second s/d region. the second s/d region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. a backside s/d contact may be connected to and extend vertically downward from a bottom surface of the second s/d region.
Inventor(s): Brent A. Anderson of Jericho VT (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, REINALDO VEGA of Mahopac NY (US) for international business machines corporation
IPC Code(s): H01L29/417, H01L21/285, H01L29/40, H01L29/45, H01L29/66, H01L29/78
Abstract: semiconductor device and methods of forming the same include a semiconductor channel. a top source/drain structure is on the semiconductor channel. a bottom source/drain structure is under the semiconductor channel. the bottom source/drain structure includes a doped semiconductor part and a conductor part, with the conductor part covering a bottom surface of the doped semiconductor part.
Inventor(s): Shogo Mochizuki of Mechanicville NY (US) for international business machines corporation, Andrew M. Greene of Slingerlands NY (US) for international business machines corporation, Gen Tsutsui of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L29/423, H01L29/06, H01L29/08, H01L29/66, H01L29/775, H01L29/786
Abstract: embodiments herein include semiconductor structures that may include a semiconductor structure for improving the switching speed of a first transistor is disclosed. the first transistor may include a first source/drain (s/d), a metal gate, a spacer between the first s/d and the metal gate, and a first nanosheet channel. the first nanosheet channel may include: a gate section with silicon-germanium (sige) surrounded by the metal gate; and a junction section comprising silicon surrounded by the spacer.
Inventor(s): Tao Li of Slingerlands NY (US) for international business machines corporation, Shogo Mochizuki of Mechanicville NY (US) for international business machines corporation, Kisik Choi of Watervliet NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L29/423, H01L21/8234, H01L23/528, H01L29/06, H01L29/786
Abstract: a semiconductor structure includes a first source-drain region; a second source-drain region; at least one channel region coupling the first and second source-drain regions; and a gate adjacent the at least one channel region. a bottom dielectric isolation region is located inward of the gate. first and second bottom silicon regions are respectively located inward of the first and second source-drain regions. a back side contact projects through the second bottom silicon region into the second source-drain region.
Inventor(s): HUIMEI ZHOU of ALBANY NY (US) for international business machines corporation, MIAOMIAO WANG of ALBANY NY (US) for international business machines corporation, Julien Frougier of ALBANY NY (US) for international business machines corporation, Andrew M. Greene of Slingerlands NY (US) for international business machines corporation, Barry Paul Linder of Hastings-on-Hudson NY (US) for international business machines corporation, Kai Zhao of ALBANY NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Tian Shen of San Jose CA (US) for international business machines corporation, Veeraraghavan S. Basker of Fremont CA (US) for international business machines corporation
IPC Code(s): H01L29/66, H01L21/768, H01L21/8234, H01L27/088, H01L29/06, H01L29/08
Abstract: an integrated circuit apparatus includes a substrate and a well contact that is disposed on the substrate. the well contact includes first and second source/drain structures that are disposed on the substrate; a metal vertical portion that contacts the substrate immediately between the first and second source/drain structures; inner spacers that electrically insulate the vertical portion from the adjacent source/drain structures; bottom dielectric isolation that electrically insulates the source/drain structures from the substrate; and a well portion that is embedded into the substrate in registry with the vertical portion. the well portion is doped differently than the substrate.
Inventor(s): Julien Frougier of Albany NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Kangguo Cheng of Schenectady NY (US) for international business machines corporation, Andrew M. Greene of Slingerlands NY (US) for international business machines corporation, Sung Dae Suk of Watervliet NY (US) for international business machines corporation
IPC Code(s): H01L29/775, H01L29/06, H01L29/423, H01L29/66
Abstract: a semiconductor device including a channel region of stacked semiconductor layers arranged in at least one cluster, wherein each cluster includes a pair of the semiconductor sheets with a dielectric material present therebetween. the semiconductor device further includes a gate structure encapsulating the channel region of stacked semiconductor sheets arranged in clusters. source and drain regions are present on opposing sides of the channel region.
Inventor(s): Brent A. Anderson of Jericho VT (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, REINALDO VEGA of Mahopac NY (US) for international business machines corporation
IPC Code(s): H01L29/78, H01L23/528, H01L23/535, H01L29/417
Abstract: a vtfet is provided on a wafer. a backside power delivery network is on a backside of the wafer. a first backside contact is connected to a bottom source/drain region of the vtfet and a first portion of the backside power delivery network. a second backside contact is connected to top source/drain region of the vtfet and a second portion of the backside power delivery network.
Inventor(s): Daniel Schmidt of Niskayuna NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Alexander Reznicek of Troy NY (US) for international business machines corporation, Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation
IPC Code(s): H01L29/786, H01L29/06
Abstract: a semiconductor device that includes a stack of sheet semiconductor layers, and source and drain regions positioned on opposing sides of a channel region in the stack of sheet semiconductor layers. a first contact is present to an upper sheet portion of the source and drain regions for the stack of sheet semiconductor layers. an extended epitaxial semiconductor region is present in contact with the lower sheet portion of the source/drain regions for the stack of sheet semiconductor layers. a second contact is present in direct contact with an upper surface of the extended epitaxial semiconductor region. a notch may be present in the upper surface of the extended semiconductor region to increase contact surface to the second contact.
Inventor(s): Mathews Thomas of Flower Mound TX (US) for international business machines corporation, Sharath Prasad Krishna Prasad of Flower Mound TX (US) for international business machines corporation, Sai Srinivas Gorti of Irving TX (US) for international business machines corporation, Amandeep Singh of Carrollton TX (US) for international business machines corporation, Dushyant K. Behl of Bangalore (IN) for international business machines corporation, Utpal Mangla of Toronto (CA) for international business machines corporation
IPC Code(s): H04B7/155, H04L67/00, H04W12/06, H04W28/08
Abstract: a communication system for a remote location, which is out of range of a telecom provider, is provided. the communication system includes a remote multi-access edge computer (rmec) proximate to the remote location and communicative with the telecom provider. the rmec is configured to run software of the telecom provider whereby the rmec is securely connectable with the telecom provider such that the rmec is capable of providing cellular connectivity to a cell phone operably deployed at the remote location.
Inventor(s): Rong Nickle Chang of Pleasantville NY (US) for international business machines corporation, Hongyi Bian of Ames IA (US) for international business machines corporation, Nitin Gaur of Round Rock TX (US) for international business machines corporation
IPC Code(s): H04L41/16, H04L41/0246, H04L43/55
Abstract: a method includes: receiving, by a processor set, a request for a web-based service; generating, by the processor set, a feature vector including values based on parameters of the request; generating, by the processor set, an endpoint selection vector including plural probabilities corresponding to plural endpoints, wherein the endpoint selection vector is generated using the feature vector with a machine learning model; selecting, by the processor set, one of the plural endpoints based on the plural probabilities; and invoking, by the processor set, the selected endpoint.
Inventor(s): ADAM PAQUIN of SUWANEE GA (US) for international business machines corporation, PEYTON DUNCAN of ORLANDO FL (US) for international business machines corporation, KEVIN SHEN of BOYDS MD (US) for international business machines corporation, JONATHAN BEES of PITTSBURGH PA (US) for international business machines corporation, SRINIVAS BABU TUMMALAPENTA of BROOMFIELD CO (US) for international business machines corporation
IPC Code(s): H04L9/40, G06F40/35, G06N3/04
Abstract: a method protects a computer asset by identifying a particular signature, which is software that causes a particular gateway to block an intrusion from reaching a particular computer asset, and installs the particular signature on the particular gateway, thus protecting the computer asset from the intrusion.
Inventor(s): Constantin Mircea Adam of Norwalk CT (US) for international business machines corporation, Muhammed Fatih Bulut of Auburndale MA (US) for international business machines corporation, Steven Ocepek of Cuyahoga Falls OH (US) for international business machines corporation
IPC Code(s): H04L9/40
Abstract: one or more systems, devices, computer program products and/or computer-implemented methods provided herein relate to prioritization of attack techniques and cyber security events. according to an embodiment, an attack prioritization engine can receive security events, train an artificial intelligence model to rank respective cyber security events as a function of risk, and output a prioritization of security events to address. a mapping component can map asset vulnerabilities to attack techniques. a calculation component can calculate and aggregate scores for respective attack techniques. an attack surface component can extract features from the aggregation of scores to rank attack techniques and determine an attack surface. the mapping component can further map security events to the attack techniques.
Inventor(s): Sudheesh S. Kairali of Kozhikode (IN) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Satyam Jakkula of BENGALURU (IN) for international business machines corporation, Sudhanshu Sekher Sar of Bangalore (IN) for international business machines corporation, Maureen Kraft of Hudson MA (US) for international business machines corporation
IPC Code(s): H04L9/40
Abstract: a method and system provide computer system security for a focus computer system (fcs). the method comprises creating a security digital twin (sdt) for the fcs with an associated security ontology for the fcs. a potential threat analyzer receives a potential threat object (pto), and maps it to an enterprise attack vector pattern. the method further comprises searching, on another computer system (ocs) for a predicted attack pattern having a similar pattern to the enterprise attack vector pattern. conditioned upon finding the predicted attack pattern, and using a potential threat handler locating an action mitigation plan (amp) related to the predicted attack pattern in the data fabric associated with the ocs, the method further comprises copying the ocs predicted attack pattern to an fcs predicted attack pattern store, copying the ocs amp to an fcs amp store, and defending the fcs from the pto using the amp.
Inventor(s): Sarbajit K. RAKSHIT of Kolkata (IN) for international business machines corporation, Katsuyuki SAKUMA of Fishkill NY (US) for international business machines corporation, Amos CAHAN of Dobbs Ferry NY (US) for international business machines corporation
IPC Code(s): H04R25/00
Abstract: method and system for a cochlear implant that includes receiving, by a processor, an electric audio signal; processing, by the processor, the electric audio signal, thereby providing a processed electric audio signal; receiving, by a transducer driver, the processed electric audio signal; transmitting, by the transducer driver, the processed electric audio signal to electro-acoustic transducer elements that are at least arranged within a cochlea; and vibrating at least one electro-acoustic transducer element of the electro-acoustic transducer elements in response to the at least one electro-acoustic transducer element receiving the processed electric audio signal, thereby providing a vibrating stimulus based on the processed electric audio signal.
Inventor(s): Sagar Tayal of Ambala City (IN) for international business machines corporation
IPC Code(s): H04W16/14, H04M15/00, H04W4/24, H04W28/02, H04W28/20
Abstract: disclosed embodiments provide techniques for dynamic radio access network sharing. in embodiments, local telecommunication infrastructure providers (ltips) and/or telecommunications operators (telcos) perform planning and infrastructure deployment, and then lease available infrastructure to telecommunications operators on a micro-location level with a radio access network exchange that allows bidding on these resources by multiple telecommunications operators. this enables opportunities to improve efficiency in terms of network resource utilization.
Inventor(s): Alfredo R Castillo of Chicago IL (US) for international business machines corporation, Akila Srinivasan of Carpentersville IL (US) for international business machines corporation
IPC Code(s): H04W28/08
Abstract: the method provides for one or more processors to disperse object data for storage within a fifth-generation radio access network (ran). the one or more processors receive radio frequency (rf) input for object data storage from a client device. the one or more processors perform a setup session configuring the rf input received for object data storage. the one or more processors perform a translation of the received rf input, wherein the translation enables processing of the rf input by an information dispersal algorithm (ida) and enables storage of the object data of the rf input among multiple next generation node base stations (gnbs) forming a gnb cluster within a radio access network (ran), and the one or more processors storing the object data of the received rf input across the gnb cluster in an object segment format.
Inventor(s): Sagar Tayal of Ambala City (IN) for international business machines corporation, Sathya Santhar of Ramapuram (IN) for international business machines corporation, Sridevi Kannan of Chennai (IN) for international business machines corporation, Nishant Satish Srivastava of Mumbai (IN) for international business machines corporation
IPC Code(s): H04W76/11
Abstract: a computer-implemented method according to one embodiment includes collecting device information from at least a first device, and receiving, from the first device, a first request to attach to a first base station. in response to receiving the first request, it is determined whether a signal broadcasted from the first base station includes public land mobile network (plmn) information of a first type of telecommunication signal. in response to a determination that the signal broadcasted from the first base station includes the plmn information, a second request is sent to a core network to connect the first device to a node associated with the first type of telecommunication signal of the first base station. in response to receiving an indication that the first device is authorized to connect, a connection is allowed to be established between the first device and the node associated with the first type of telecommunication signal.
Inventor(s): Brent A. Anderson of Jericho VT (US) for international business machines corporation, Theodorus E. Standaert of Clifton Park NY (US) for international business machines corporation, Junli Wang of Slingerlands NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L27/22, H01L27/24, H01L43/12, H01L45/00
Abstract: semiconductor devices and methods of forming the same include a front-end-of-line (feol) layer that includes a first transistor device. a first back-end-of-line (beol) layer is on a front side of the feol layer and includes a first electrical connection to the first transistor device. a second beol layer is on a back side of the feol layer and includes a first beol device with a second electrical connection to the first transistor device.
Inventor(s): Victor W.C. Chan of Guilderland NY (US) for international business machines corporation, JIN PING HAN of Yorktown Heights NY (US) for international business machines corporation, Samuel Sung Shik Choi of Ballston Lake NY (US) for international business machines corporation, Injo Ok of Loudonville NY (US) for international business machines corporation
IPC Code(s): H01L45/00, H01L27/24
Abstract: an integrated circuit includes a field effect transistor (fet) and a phase change memory (pcm) cell. the pcm cell includes a heater, wherein a bottom surface of the heater is at or below a top surface of the fet.
International Business Machines Corporation patent applications on April 4th, 2024
- International Business Machines Corporation
- G05D1/10
- B64C39/02
- G06Q10/08
- International business machines corporation
- G06F3/06
- G06F8/65
- G06F9/48
- G06F9/4401
- G06F1/3212
- G06F9/445
- G06F9/455
- G06F9/30
- G06F11/36
- G06F9/50
- G06F8/36
- G06F11/20
- G06F11/07
- G06F11/30
- G06F16/16
- G06F16/13
- G06F16/172
- G06F16/2455
- G06F11/34
- G06F16/22
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