International Business Machines Corporation patent applications on April 11th, 2024
Patent Applications by International Business Machines Corporation on April 11th, 2024
International Business Machines Corporation: 52 patent applications
International Business Machines Corporation has applied for patents in the areas of G06N20/00 (10), H01L29/775 (6), G06N3/08 (6), G06F40/20 (4), H01L29/06 (3)
With keywords such as: data, computer, based, layer, signal, program, training, language, document, and features in patent application abstracts.
Patent Applications by International Business Machines Corporation
Inventor(s): Nathan Jon Rauh of Rochester MN (US) for international business machines corporation, Alex Seitzinger Motley of Rochester MN (US) for international business machines corporation, Mark Swatosh of ROCHESTER MN (US) for international business machines corporation, James Stephens of Palisade MN (US) for international business machines corporation
IPC Code(s): G06F3/06
Abstract: a computer implemented method manages connections in a connection pool. a computer system creates a modified call stack for a connection request in response to receiving the connection request. the modified call stack comprises elements that call prepared statements that are part of an application logic for the connection request. the computer system identifies a group of potential connections from the connections in the connection pool matching the connection request. the group of potential connections is associated with a group of associated modified call stacks that call the prepared statements. the computer system determines a group of weighted match scores for the group of associated modified call stacks from a comparison of the modified call stack with the group of associated modified call stacks. the computer system selects a connection from the group of potential connections based on a highest weighted match score in the group of weighted match scores.
Inventor(s): DANIEL TARASEK of Krakow (PL) for international business machines corporation, Lukasz Janus of Krakow (PL) for international business machines corporation
IPC Code(s): G06F11/34, G06F9/455
Abstract: the present disclosure relates to method for monitoring a computer system. the computer system comprises a first processing unit and a monitoring unit for monitoring operation of the computer system. the method comprises: providing the computer system with a converter unit that is configured to communicate with the monitoring unit and the first processing unit. the converter unit may receive monitoring data from the monitoring unit. the received monitoring data may be pre-processed at the converter unit. the converter unit may send the resulting pre-processed data to at least one remote management system.
Inventor(s): Ekaterina M. Ambroladze of Somers NY (US) for international business machines corporation, Matthias Klein of POUGHKEEPSIE NY (US) for international business machines corporation, Sascha Junghans of Ammerbuch (DE) for international business machines corporation, Kevin Lopes of Wallkill NY (US) for international business machines corporation
IPC Code(s): G06F12/0802, G06F13/16
Abstract: a data processing system includes a system fabric coupling a coherence manager and an input/output (i/o) requestor. the i/o requestor issues a first snoop request of a first i/o store operation and a subsequent second snoop request of a second i/o store operation. each of the first and second snoop requests specifies an update to a respective storage location identified by a coherent memory address. the i/o requestor receives respective ownership coherence responses for each of the first and second i/o store operations. the respective first and second ownership coherence responses indicate the coherence manager has concurrent coherence ownership of the memory address for both the first and second i/o store operations. in response to receipt of each of the ownership coherence responses, the i/o requestor issues respective first and second execute coherence responses to command the coherence manager to initiate updates to the respective storage locations.
Inventor(s): SASCHA JUNGHANS of AMMERBUCH (DE) for international business machines corporation, MATTHIAS KLEIN of POUGHKEEPSIE NY (US) for international business machines corporation, JULIAN HEYNE of STUTTGART (DE) for international business machines corporation, NORBERT HAGSPIEL of TUEBINGEN (DE) for international business machines corporation, FAHMIYAH SAMAD of STUTTGART (DE) for international business machines corporation, ANANTH GARIKAPATI of STUTTGART (DE) for international business machines corporation
IPC Code(s): G06F13/16, G06F13/40, G06F13/42
Abstract: combining pcie partial store commands along cache line boundaries, including: receiving a plurality of peripheral component interface express (pcie) packets; splitting the plurality of pcie packets along cache line boundaries to generate a plurality of partial store commands; and combining one or more sets of partial store commands to generate one or more combined partial store commands aligned to the cache line boundaries.
Inventor(s): Varun Ojha of Panchkula (IN) for international business machines corporation, Ana C. Biazetti of Cary NC (US) for international business machines corporation, Ritesh Tandon of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F16/23, G06F16/27
Abstract: a computer-implemented method, system and computer program product for preserving concurrency and asynchronous execution for versioned documents. a versioned document is received to be uploaded onto a platform, such as a blockchain platform, where the metadata of the versioned document includes a first identifier representing a time at which the version of the versioned document came into existence. furthermore, a second identifier is generated representing a specific state or instance of the versioned document with no relation to a logical order of the instance of the versioned document with respect to other versions of the versioned document. a document record may then be created for the versioned document which includes both identifiers. such identifiers may be utilized by a distributed application, such as a blockchain application, to handle various types of requests from the users of the client devices while still preserving concurrency and asynchronous execution for versioned documents.
Inventor(s): Kevin Males of Kings Lynn (GB) for international business machines corporation, Alistair James Brain of Cambridge (GB) for international business machines corporation
IPC Code(s): G06F16/338, G06F40/20
Abstract: provided are a computer program product, system, and method for sorting documents according to comprehensibility scores determined for the documents. a document has sections of text associated with topics. a determination is made of familiarity scores for a user for the topics associated with the sections of text in the document. a determination is made of a comprehensibility score of the document, indicating comprehensibility of the document to the user, as a function of the determined familiarity scores for the topics in the document. the comprehensibility score for the document is used to determine an order in which to present the document to the user with a group of documents.
Inventor(s): Alexander Merschel of Stuttgart (DE) for international business machines corporation, Nehal Dudani of Hamburg (DE) for international business machines corporation, Dennis Butterstein of Stuttgart (DE) for international business machines corporation, Martin Anton Oberhofer of Sindelfingen (DE) for international business machines corporation, Thomas Schwarz of Stuttgart (DE) for international business machines corporation, Tobias Kevin Fränzel of Tuebingen (DE) for international business machines corporation
IPC Code(s): G06F16/901, G06F16/906
Abstract: a method, computer system, and a computer program product for storing a graph is provided. the present invention may include providing a key-value store. the present invention may include storing a graph in the key-value store, wherein storing a specific node of the graph in the key-value store comprises: storing, as a key, identifiers of the specific node and of k-hop neighborhood of the specific node, and as value of the key, attribute values of the specific node, wherein the k-hop neighborhood of the specific node comprises a set of neighboring nodes that are reachable from the specific node within k edges.
Inventor(s): Susan Hallen of Chicago IL (US) for international business machines corporation, Rose Fleischman of Poughkeepsie NY (US) for international business machines corporation, Alan Daet Mejía Villaseñor of Guadalajara (MX) for international business machines corporation, Diane Helen Wasserstrom of Poughkeepsie NY (US) for international business machines corporation
IPC Code(s): G06F16/9032, G06F16/93, G06F40/20
Abstract: methods, systems, and computer program products for enhanced document ingestion using natural language processing are provided herein. a computer-implemented method includes identifying, within a first document, terms unknown to a first natural language processing model by processing the first document using the first natural language processing model; identifying, within a second document, terms known to a second natural language processing model by processing the second document using the second natural language processing model; comparing the terms unknown to the first natural language processing model to the terms known to the second natural language processing model; and upon determining that at least one of the terms unknown to the first natural language processing model matches at least one of the terms known to the second natural language processing model, reprocessing the first document using the second natural language processing model.
Inventor(s): David Alvra Wood, III of Scarsdale NY (US) for international business machines corporation, Petros Zerfos of New York NY (US) for international business machines corporation, Syed Yousaf Shah of Yorktown Heights NY (US) for international business machines corporation
IPC Code(s): G06F17/18, G06Q10/04
Abstract: a method of detecting seasonality in time series data includes receiving a set of time series data, analyzing the time series data to generate a power spectrum, the power spectrum indicative of power as a function of frequency, and selecting a peak in the power spectrum, the selected peak having a peak power. the method also includes performing an interpolation around the selected peak, and selecting a number of additional peaks having powers within a selected proportion of the peak power. the method further includes, based on the number of additional peaks being less than a threshold number, identifying the selected peak as representing a season having a seasonal length, and determining a seasonal length of the season based on a frequency at the identified peak.
Inventor(s): Matthias Seul of Folsom CA (US) for international business machines corporation, Andrea Giovannini of Zurich (CH) for international business machines corporation, Frederik Frank Flother of Schlieren (CH) for international business machines corporation, Tim Uwe Scheideler of Schoenenberg (CH) for international business machines corporation
IPC Code(s): G06F21/52, G06N20/00
Abstract: a computer-implemented method or protecting a machine-learning model against training data attacks is disclosed. the method comprises performing an initial training of a machine-learning system with controlled training data, thereby building a trained initial machine-learning model and identifying high-impact training data from a larger training data set than in the controlled training data, wherein the identified individual training data have an impact on a training cycle of the training of machine-learning model, wherein the impact is larger than a predefined impact threshold value. the method also comprises building an artificial pseudo-malicious training data set from the identified high-impact training data and retraining the machine-learning system comprising the trained initial machine-learning model using the artificial pseudo-malicious training data set.
Inventor(s): Su Liu of Austin TX (US) for international business machines corporation, SARITHA ARUNKUMAR of () for international business machines corporation, Boyi Tzen of () for international business machines corporation, Luis Osvaldo Pizana of Austin TX (US) for international business machines corporation
IPC Code(s): G06F21/56
Abstract: a computer implemented method, apparatus, system, and computer program product detects a problematic source code. a computer system loads a source code into a first memory. the computer system loads a rendered source code into a second memory. the rendered source code is a rendered version of the source code. the computer system determines a difference between the source code in the first memory and the rendered source code in the second memory. the computer system determines whether a problematic source code is present within the source code using the difference. the computer system performs a set of actions with respect to the problematic source code in response to determining that the problematic source code is present in the source code. according to other illustrative embodiments, a computer system and a computer program product for detecting a problematic source code are provided.
Inventor(s): Eric John Bartlett of Chard (GB) for international business machines corporation, Dominic Tomkins of Alton (GB) for international business machines corporation, MILES MULHOLLAND of Eastleigh (GB) for international business machines corporation, Alex Dicks of Winchester (GB) for international business machines corporation
IPC Code(s): G06F21/60, G06F3/06
Abstract: a method, system, and computer program product for managing a storage array in a storage system, the storage array comprising a first and second data blocks comprising: receiving a set of cryptographic values from the storage array, the set comprising a first value associated with the first data block, and a second value associated with the second data block; analysing the set of cryptographic values to determine a set of associations, the set of associations comprising a first association between the first data block and the second data block, storing the set of associations; and in response to determining the set of associations, performing a storage management operation on at least one of the first data block and the second data block.
Inventor(s): SheshaShayee K Raghunathan of Bangalore (IN) for international business machines corporation, Charles Gates of Poughkeepsie NY (US) for international business machines corporation, Kerim Kalafala of Rhinebeck NY (US) for international business machines corporation, Steven Joseph Kurtz of Austin TX (US) for international business machines corporation, Morgan D. Davis of Rochester MN (US) for international business machines corporation, Debra Dean of Cary NC (US) for international business machines corporation, Chris Cavitt of Queensbury NY (US) for international business machines corporation, Chaitra M Bhat of Bangalore (IN) for international business machines corporation, Richard William Taggart of Poughkeepsie NY (US) for international business machines corporation
IPC Code(s): G06F30/31, G06F30/398
Abstract: a computer-implemented method, system and computer program product for recommending design changes in designing a digital integrated circuit. an analysis of the digital integrated circuit being designed is performed, where the result of such an analysis involves violations being identified and stored. a stored violation, such as a cross-domain, cross-hierarchy and multi-cycle violation, may then be analyzed to identify a root cause of the violation using a rule. such a rule may be used for triaging various failures in the cross-domain, cross-hierarchy and/or multi-cycle violation of the digital integrated circuit. a design change in the design of the digital integrated circuit may then be recommended based on the identified root cause of the violation. in this manner, the root cause of failures are effectively identified in the design of digital integrated circuits using an offline analysis of cross-domain, cross-hierarchy and/or multi-cycle violations using a rules-based approach.
Inventor(s): Yang Zhao of Tokyo (JP) for international business machines corporation, Issei Yoshida of Setagaya-ku (JP) for international business machines corporation
IPC Code(s): G06F40/51, G06F40/44
Abstract: methods and systems for sentence acceptability judgment. a word frequency distribution for a predetermined textual data set is obtained. a replacement rate is determined based on an obtained word frequency distribution for a predetermined textual data set and every occurrence of a word having a frequency lower than the replacement rate is replaced in text of a training data set with a corresponding tag to generate revised text of the training data set (the training data set comprising at least a portion of the predetermined textual data set). a plurality of language models are trained with the revised text and a best performing trained language model of the plurality of trained language models is selected. an acceptability of each sentence of a plurality of candidate sentences is rated using the selected trained language model and a best sentence of the plurality of candidate sentences is selected based on the ratings.
Inventor(s): Kavitha Hassan YOGARAJ of Bangalore (IN) for international business machines corporation, Shantanu SINHA of Kolkata (IN) for international business machines corporation, Amit Kumar RAHA of Kolkata (IN) for international business machines corporation, Shikhar KWATRA of San Jose CA (US) for international business machines corporation, Debajyoti BAGCHI of Kolkata (IN) for international business machines corporation, Aaron K. BAUGHMAN of Cary NC (US) for international business machines corporation
IPC Code(s): G06N3/04
Abstract: provided are techniques for enhancing silent features with adversarial networks for improved model versions. input features are obtained. hidden features are identified. quantum feature importance scoring is performed to assign an importance score to each of the hidden features. silent features are identified as the hidden features with the importance score below a first threshold. important features are identified as the input features and as the hidden features with the importance score above a second threshold. a silent feature model is built using the silent features. an important feature model is built using the important features. an ensemble model is built with the silent feature model and the important feature model. the ensemble model is used to generate one or more predictions and one or more prescriptions.
Inventor(s): Lam Minh Nguyen of Ossining NY (US) for international business machines corporation
IPC Code(s): G06N3/08
Abstract: select an initial weight vector for a convex optimization sub-problem associated with a neural network having a non-convex network architecture loss surface. with at least one processor, approximate a solution to the convex optimization sub-problem that obtains a search direction, to learn a common classifier from training data. with the at least one processor, update the initial weight vector by subtracting the approximate solution to the convex optimization sub-problem times a first learning rate. with the at least one processor, repeat the approximating and updating steps, for a plurality of iterations, with the updated weight vector from a given one of the iterations taken as the initial weight vector for a next one of the iterations, to obtain a final weight vector for the neural network, until convergence to a global minimum is achieved, to implement the common classifier.
Inventor(s): Zhong Fang Yuan of Xi'an (CN) for international business machines corporation, Si Tong Zhao of Beijing (CN) for international business machines corporation, Tong Liu of XI'AN (CN) for international business machines corporation, Yi Chen Zhong of Shanghai (CN) for international business machines corporation, Yuan Yuan Ding of Shanghai (CN) for international business machines corporation, Hai Bo Zou of Beijing (CN) for international business machines corporation
IPC Code(s): G06N3/08, G06N3/04
Abstract: a method for contrastive learning by selecting dropout ratios and locations based on reinforcement learning includes receiving training data having a positive sample corresponding to a target and negative samples not corresponding to the target. a dropout policy for a neural network is produced based on the training data, where the dropout policy identifies at least one connection between neurons in the neural network to dropout. the training data is encoded, based on the dropout policy, to form embeddings, where the embeddings include multiple positive sample embeddings corresponding to the positive sample and multiple negative sample embedding corresponding to the negative samples.
Inventor(s): MATTIA RIGOTTI of BASEL (CH) for international business machines corporation, IOANA GIURGIU of ZURICH (CH) for international business machines corporation, THOMAS GSCHWIND of ZURICH (CH) for international business machines corporation, CHRISTOPH ADRIAN MIKSOVIC CZASCH of ZURICH (CH) for international business machines corporation, PAOLO SCOTTON of RUESCHLIKON (CH) for international business machines corporation
IPC Code(s): G06N3/08
Abstract: generating a neural network model for producing explainable prediction outputs for input data samples is provided. training dataset of data samples are provided, each having a prediction label indicating a desired prediction output from the model for that sample, and a set of concept vectors are defined comprising a plurality of concept vectors which are associated with respective predefined concepts characterizing information content of the data samples. a set of input vectors are produced from each data sample. a neural network model is trained that includes a cross-attention module for producing a sample embedding for a data sample and a prediction module for producing a prediction output from the sample embedding.
Inventor(s): Nhan Huu Pham of Tarrytown NY (US) for international business machines corporation, Lam Minh Nguyen of Ossining NY (US) for international business machines corporation, Jie Chen of Briarcliff Manor NY (US) for international business machines corporation, Thanh Lam Hoang of Maynooth (IE) for international business machines corporation, Subhro Das of Cambridge MA (US) for international business machines corporation
IPC Code(s): G06N3/092
Abstract: in aspects of the disclosure, a method comprises training, by a computing system, a dynamics model of a cooperative multi-agent reinforcement learning (c-marl) environment. the method further comprises processing, by the computing system, a perturbation optimizer to generate a state perturbation of the c-marl environment, based on the dynamics model. the method further comprises selecting one or more agents of the c-marl system as having enhanced vulnerability. the method further comprises attacking, by the computing system, the c-marl system based on the state perturbation and the selected one or more agents.
Inventor(s): Stefan WOERNER of Zurich (CH) for international business machines corporation, Panagiotis BARKOUTSOS of Zurich (CH) for international business machines corporation, Ivano TAVERNELLI of Zurich (CH) for international business machines corporation
IPC Code(s): G06N7/08, G06F9/38, G06F9/50, G06F15/16, G06F17/11, G06N10/00
Abstract: techniques for facilitating utilizing a quantum computing circuit in conjunction with a stochastic control problem are provided. in one embodiment, a system is provided that comprises a quantum computing circuit that prepares a quantum state that represents a stochastic control problem. the system can further comprise a classical computing device that determines parameters for the quantum computing circuit.
Inventor(s): Daniel Miller of Wädenswil (CH) for international business machines corporation, Laurin Elias Fischer of Zürich (CH) for international business machines corporation, Panagiotis Barkoutsos of Zurich (CH) for international business machines corporation, Francesco Tacchino of Rueschlikon (CH) for international business machines corporation, Daniel Josef Egger of Thalwil (CH) for international business machines corporation, Ivano Tavernelli of Wädenswil (CH) for international business machines corporation
IPC Code(s): G06N10/20
Abstract: the present disclosure relates to a quantum system of dimension m comprising a transmon device. the transmon device is in an initial state �which is restricted to a state �of a n-dimensional quantum system embedded in the quantum system, where n<m. the transmon device is configured to receive a sequence of pulses for transforming the initial state �to a state �of the quantum system. the transmon device is connected to a readout that is configured to perform a projection-valued measure (pvm) of the transmon device in its state �.
Inventor(s): Baleegh Abdo of Fishkill NY (US) for international business machines corporation
IPC Code(s): G06N10/40
Abstract: a device comprises a nondegenerate through quantum-limited amplifier comprising a first port, a second port, and a third port. the first port is configured to receive first quantum signals which comprise frequencies within a first frequency band. the second port is configured to receive second quantum signals which comprise frequencies within a second frequency band, which is non-overlapping with the first frequency band. the nondegenerate through quantum-limited amplifier is configured to amplify the first quantum signals, amplify and convert the frequencies of the second quantum signals to frequencies within the first frequency band, and output the amplified first quantum signals and the amplified frequency-converted second quantum signals from the third port.
Inventor(s): John S. WERNER of Fishkill NY (US) for international business machines corporation, Arkadiy O. TSFASMAN of Wappingers Falls NY (US) for international business machines corporation, Dane WARREN of Highland NY (US) for international business machines corporation, Charles BENE of Poughkeepsie NY (US) for international business machines corporation, Ryan MULHERN of Mahopac NY (US) for international business machines corporation, Thomas C. REED of Tucson AZ (US) for international business machines corporation
IPC Code(s): G06N20/00, G06K9/62
Abstract: machine learning-based part selection in relation to one or more end use environmental conditions is provided. the process includes training a machine learning model to facilitate evaluation of a part for use in a product based on an environmental condition. further, the process includes receiving measurement data for the part, and establishing a score for the part by comparing the measurement data for the part to a specification for the part. in addition, the method includes using the machine learning model and the established score for the part in determining whether to use the part in the product based on the environmental condition.
Inventor(s): Harish Bharti of Pune (IN) for international business machines corporation, Rajesh Kumar Saxena of Thane East (IN) for international business machines corporation, Jayadev J of Kasaragod (IN) for international business machines corporation, Sandeep Sukhija of Rajasthan (IN) for international business machines corporation
IPC Code(s): G06N20/00, G06K9/62, G06Q10/06
Abstract: prioritizing a work request pertaining to a physical asset can include generating a data structure that encodes the work request as a multidimensional representation indicating at least one classification, each at least one classification including at least one sub-category. in response to identifying multiple work requests encoded as multidimensional representations with respect to the physical asset, each multidimensional representation can be reduced to a one-dimensional (1-d) representation that preserves a variance factor of each sub-category of each multidimensional representation. each 1-d structure can be input to a machine learning model trained to prioritize each of the work requests. the work requests can be prioritized in accordance with the machine learning model based on the 1-d structures. the priorities of each of the work requests can be output.
Inventor(s): Soyeon Park of Gyeongsangbuk-Do (KR) for international business machines corporation, Dhilung Kirat of Hartsdale NY (US) for international business machines corporation, Sanjeev Das of White Plains NY (US) for international business machines corporation, Douglas Lee Schales of Ardsley NY (US) for international business machines corporation, Taesung Lee of Ridgefield CT (US) for international business machines corporation, Jiyong Jang of Chappaqua NY (US) for international business machines corporation
IPC Code(s): G06N20/00, G06K9/62
Abstract: a computer-implemented method according to one embodiment includes training a bidirectional encoder representations from transformers (bert) model to generate a software representation. an intermediate representation (ir) of a software package is input to the trained bert model, and a software representation corresponding to the software package is received as output from the trained bert model. a computer program product according to another embodiment includes a computer readable storage medium having program instructions embodied therewith. the program instructions are readable and/or executable by a computer to cause the computer to perform the foregoing method. a system according to another embodiment includes a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. the logic is configured to perform the foregoing method.
Inventor(s): He Sheng Yang of Beijing (CN) for international business machines corporation, Mo Chi Liu of Beijing (CN) for international business machines corporation, Yun Wang of Beijing (CN) for international business machines corporation, Hong Wei Jia of Beijing (CN) for international business machines corporation, Wu Yan of San Jose CA (US) for international business machines corporation, Xiaoyang Yang of San Francisco CA (US) for international business machines corporation
IPC Code(s): G06N20/00
Abstract: according to an aspect, a computer-implemented method includes accessing a profile of a user that indicates a likelihood that the user will execute each of a plurality of types of processing when training a new ai model. a runtime matrix that includes identifiers of runtime environments is accessed. the matrix also includes, for each of the runtime environments, a frequency of use of the runtime environment to train previously trained ai models using each of the plurality of types of processing. one or more of the runtime environments is selected for output to the user based at least in part on the profile of the user and the runtime matrix. identifiers of the selected one or more of the runtime environments are output to a user interface of the user along with a suggestion to use one of the selected one or more of the runtime environments.
Inventor(s): Phillip Gregory LOPEZ of Poughkeepsie NY (US) for international business machines corporation, Jung Wook PARK of Poughkeepsie NY (US) for international business machines corporation, David C. REED of Tucson AZ (US) for international business machines corporation, Elliott PICKER of New Hamburg NY (US) for international business machines corporation
IPC Code(s): G06Q10/06
Abstract: a method, system, and computer program product are disclosed for implementing enhanced expertise and evidence based decision making in knowledge-based applications. expertise and evidence based decision making operations include differentiating between an average user and an expert user, and using real time feedback from expert users to update and embed expert knowledge into a predefined baseline command sequence model for a given task or problem.
Inventor(s): Pavan Kumar Penugonda of Anakapalle (IN) for international business machines corporation, Saraswathi Sailaja Perumalla of Visakhapatnam (IN) for international business machines corporation, Venkata Ratnam Alubelli of Visakhapatnam (IN) for international business machines corporation, Avinash Reddy Devireddy of Hyderabad (IN) for international business machines corporation
IPC Code(s): G06Q30/0282
Abstract: computer implemented method, systems, and computer program products include program code executing on a processor(s) that determines that a user has purchased a product. the program code classifies, with at least one trained algorithm, the product into a product type classification. the program code implements one or more trigger events; based on each trigger event occurring, the processor(s) generates and transmits an inquiry to the user. the program code determines that a trigger event has occurred. the program code generates the inquiry, obtains responsive feedback, and generates a product review.
Inventor(s): Raghuveer Prasad Nagar of Kota (IN) for international business machines corporation, Subba Rayudu Tangirala of Bangalore (IN) for international business machines corporation, Abhishek Solanki of LUCKNOW (IN) for international business machines corporation, Jagadesh Ramaswamy Hulugundi of Bangalore (IN) for international business machines corporation
IPC Code(s): G06Q30/02
Abstract: according to one embodiment, a method, computer system, and computer program product for utilizing a pricing engine is provided. the present invention may include analyzing pricing factors of one or more products in an online listing; recommending a best price proposal to list the one or more products based on the analyzed pricing factors; analyzing buyer factors of a potential buyer; and recalculating the best price proposal based on the analyzed buyer factors.
Inventor(s): Atul Mene of Morrisville NC (US) for international business machines corporation, Michael Boone of Lutz FL (US) for international business machines corporation, Tushar Agrawal of West Fargo ND (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G06Q50/02, G06Q30/02, G06V20/10, G06V20/13
Abstract: a method is provided for identifying topography in a locality. the topography includes horizontal surfaces and vertical surfaces. sunlight exposure incident to the identified topography is identified. the intensity of the identified sunlight exposure and variation over time is analysed. crop types for growing on the topography based on the analysed intensity of sunlight exposure and variation over time are identified.
Inventor(s): Xue Ping Liu of Beijing (CN) for international business machines corporation, Fei Wang of Dalian (CN) for international business machines corporation, Dan Zhang of Beijing (CN) for international business machines corporation, Kun Yan Yin of Ningbo (CN) for international business machines corporation, Yun Jing Zhao of Beijing (CN) for international business machines corporation, Jian Long Sun of Langfang (CN) for international business machines corporation, Zhi Xing Peng of Beijing (CN) for international business machines corporation
IPC Code(s): G06T5/20, G06F16/901, G06T17/00
Abstract: one or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to detecting a closed ring in a three-dimensional (3d) point cloud via cycle basis. a system can comprise a memory configured to store computer executable components; and a processor configured to execute the computer executable components stored in the memory, wherein the computer executable components can comprise a filtering component that can filter a first undirected graph of a three-dimensional (3d) point cloud, by eliminating one or more edges of the first undirected graph that are longer than an adaptive threshold, wherein filtering the first undirected graph can produce a second undirected graph; and a detection component that can detect a minimum cycle basis of the second undirected graph to determine a cycle path that can traverse an irregular annular shape that is represented by the 3d point cloud.
Inventor(s): HAOXIANG QIU of Tokyo (JP) for international business machines corporation, TADANOBU INOUE of Yokohama (JP) for international business machines corporation, Takayuki Katsuki of Tokyo (JP) for international business machines corporation, RYUKI TACHIBANA of Tokyo (JP) for international business machines corporation
IPC Code(s): G06T7/00, G06T7/11
Abstract: one or more systems, devices, computer program products, and/or computer-implemented methods provided herein relate to accurate anomaly detection in images using patched features. according to an embodiment, an extraction component can extract multiple layers of features from one or more patches of an image using a pretrained convolutional neural network (cnn). a feature mapping component can concatenate the features from the multiple layers to generate a tensor feature map comprising a one-dimensional feature vector for respective patches. a cropping component can perform center cropping on the tensor feature map. a calculation component can calculate a distance to a feature distribution mean for respective patches.
Inventor(s): Sudheesh S. Kairali of Kozhikode (IN) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G06T7/00, G01M99/00, G06T7/60
Abstract: a system, method, and computer program product perform audio-visual inspection at a surface of a liquid over machinery that is operating under the surface. the audio-visual inspection includes each of feeding surface wave movements into a neural network, feeding bubble formation pattern into the neural network, feeding bubble dimensions into the neural network, and feeding underwater acoustic information to the neural network. the system, method, and computer program product further identify, using the neural network, a statistical anomaly from the audio-visual inspection indicating an anomaly of the performance of the machinery.
Inventor(s): Bibhudatta Mohapatra of Thanisandra (IN) for international business machines corporation
IPC Code(s): G06T11/60
Abstract: a computer implemented method for manipulating an image comprising pixels. a group of processor units creates editable text having changeable text attributes from text in the image. the group of processor units forms a text layer for the image with the editable text created from the text in the image, wherein the editable text is located in text positions in the text layer corresponding to positions of the text in the image. the group of processor units creates a set of editable shapes having changeable shape attributes, wherein the set of editable shapes correspond to a set of shapes in the image. the group of processor units forms a shape layer for the image with the set of editable shapes. the set of editable shapes have a set of shape positions in the shape layer that correspond to a set of positions of the set of shapes in the image.
Inventor(s): Wei Jun Zheng of Shanghai (CN) for international business machines corporation, Xiao Xia Mao of Shanghai (CN) for international business machines corporation, QING LU of Shanghai (CN) for international business machines corporation, Yuan Jin of Shanghai (CN) for international business machines corporation, Xiao Feng Ji of Shanghai (CN) for international business machines corporation
IPC Code(s): G09B19/06, G09B5/06, G10L13/08, G10L25/18
Abstract: a method, computer system, and a computer program product for syllable-based pronunciation help are provided. an input text in a first language may be received. a selection of a target language that is different from the first language may be received. from the target language, syllables with a pronunciation most closely matching a pronunciation of the input text in the first language are obtained. the obtaining is based on a comparison of one or more spectrograms for the input text with one or more spectrograms for text of the target language. the obtained syllables in the target language are presented.
Inventor(s): Ghazi Sarwat Syed of Zurich (CH) for international business machines corporation, Abu Sebastian of Adliswil (CH) for international business machines corporation
IPC Code(s): G11C11/42, G11C11/56, G11C15/04
Abstract: photonic content-addressable memories (cams) and applications thereof are provided. the cam includes a photonic cross-bar array comprising a plurality of row and column waveguides, and a plurality of photonic filter devices. each filter device is selectively programmable in first and second states representing respective stored bit values that filters out light according to the programming. an encoder for encoding a plurality of input bit-strings into optical signals such that bit values in different bit-strings are encoded using optical signals in different pairs of optical states, and to simultaneously supply the optical signals corresponding to each bit-position in the bit-strings to a respective row waveguide of the array. the cam further comprises a detector for detecting light in any of said optical states in each column waveguide, thereby identifying any mismatch between each input bit-string and bit values stored in the filter devices coupling light to that waveguide.
Inventor(s): Albert M. Chu of Nashua NH (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Huai Huang of Clifton Park NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L23/48, H01L21/8234, H01L27/088, H01L29/06, H01L29/08, H01L29/66, H01L29/775, H01L29/786
Abstract: a semiconductor device includes backside power rails located between n channel field effect transistor to n channel field effect transistor spaces, and between at least one p channel field effect transistor to p channel field effect transistor space; and backside local signal lines located between the backside power rails.
Inventor(s): Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation
IPC Code(s): H01L23/522, H01L21/306, H01L21/3205, H01L23/528
Abstract: a semiconductor structure is presented including a first level of interconnect wiring, a second level of interconnect wiring disposed above the first level of interconnect wiring, a third level of interconnect wiring disposed above the second level of interconnect wiring, and a skip via extending from the third level of interconnect wiring to the first level of interconnect wiring such that a sidewall of the skip via maintains electrical contact with the second level of interconnect wiring. a contact area between the sidewall of the skip via and the second level of interconnect wiring is greater than a contact area between a bottom portion of the skip via and a top portion of the first level of interconnect wiring.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Kangguo Cheng of Schenectady NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Min Gyu Sung of Latham NY (US) for international business machines corporation
IPC Code(s): H01L49/02
Abstract: a semiconductor structure includes a capacitor structure at least partially disposed in a trench of an interlayer dielectric layer. the capacitor structure includes first and second electrode layers separated by a dielectric layer. a top surface of the first electrode layer is below a top surface of the second electrode layer and the dielectric layer. a spacer is disposed on the first electrode layer and a contact is disposed in the trench and connected to the second electrode layer and the spacer.
Inventor(s): Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Kisik Choi of Watervliet NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L23/48, H01L29/417, H01L29/775, H01L29/786
Abstract: a semiconductor structure includes a shallow trench isolation region disposed within a semiconductor substrate, and a conductive spacer disposed within the shallow trench isolation region.
Inventor(s): Chen Zhang of Guilderland NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Shogo Mochizuki of Mechanicville NY (US) for international business machines corporation, Tenko Yamashita of Schenectady NY (US) for international business machines corporation
IPC Code(s): H01L29/08, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
Abstract: embodiments of present invention provide a semiconductor structure. the semiconductor structure includes a first nanosheet transistor having a first source/drain (s/d) region; and a second nanosheet transistor on top of the first nanosheet transistor, the second nanosheet transistor having a second s/d region, the second s/d region being separated from the first s/d region by a dielectric cap layer, wherein the first s/d region of the first nanosheet transistor has a substantially flat top surface adjacent to the dielectric cap layer and has at least one vertical edge that is substantially aligned with an edge of the dielectric cap layer. a method of manufacturing the semiconductor structure is also provided.
Inventor(s): Keiji Matsumoto of Yokohama-shi (JP) for international business machines corporation, Mukta Ghate Farooq of HOPEWELL JCT NY (US) for international business machines corporation, John Knickerbocker of Monroe NY (US) for international business machines corporation
IPC Code(s): H01S5/024, H01L23/367, H01L23/373
Abstract: a heat spreader apparatus includes a first portion; a second portion; and a connecting portion between the first and second portions, with high-conductivity axes and a low-conductivity axis, the low-conductivity axis being directed between the first and second portions. in one or more embodiments, the first, second, and connecting portions are thermally anisotropic blocks, and the apparatus forms a rectangular prism.
Inventor(s): David J. KROLAK of Rochester MN (US) for international business machines corporation, Daniel Mark DREPS of Georgetown TX (US) for international business machines corporation, Erik ENGLISH of Salt Point NY (US) for international business machines corporation, Jieming QI of Austin TX (US) for international business machines corporation, Michael SPERLING of Poughkeepsie NY (US) for international business machines corporation
IPC Code(s): H04B15/00, H04L7/00
Abstract: method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting, by a first counter, a clock signal; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first selection signal to a first selection signal input of the transmitter multiplexer; and alternately transmitting, in response to the first selection signal and by a first digital data signal output of the transmitter multiplexer, the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver, the receiver and the digital data signal output operably coupled to a data link.
Inventor(s): David J. KROLAK of Rochester MN (US) for international business machines corporation, Daniel Mark DREPS of Georgetown TX (US) for international business machines corporation, Erik ENGLISH of Salt Point NY (US) for international business machines corporation, Jieming QI of Austin TX (US) for international business machines corporation, Michael SPERLING of Poughkeepsie NY (US) for international business machines corporation
IPC Code(s): H04L7/00
Abstract: method and apparatus for transferring a data signal including receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting, by a digital data signal output of the multiplexer, the digital data signal to a receiver that is operably coupled to the data link; receiving, by a selection signal input of the multiplexer, a first selection signal that indicates an idle mode for the transmitter; receiving, by a second input of the multiplexer, a patterned data signal; and transmitting, by the digital data signal output and in response to the first selection signal, the patterned data signal to the receiver.
Inventor(s): Allon Adir of Kiryat Tivon (IL) for international business machines corporation, Ramy Masalha of Kafr Qari (IL) for international business machines corporation, Eyal Kushnir of Kfar Vradim (IL) for international business machines corporation, OMRI SOCEANU of Haifa (IL) for international business machines corporation, Ehud Aharoni of Kfar Saba (IL) for international business machines corporation, Nir Drucker of Zichron Yaakov (IL) for international business machines corporation, GUY MOSHKOWICH of Nes Ziyona (IL) for international business machines corporation
IPC Code(s): H04L9/00, G06F9/38, H04L9/40
Abstract: mechanisms are provided for fully homomorphic encryption enabled graph embedding. an encrypted graph data structure, having encrypted entities and predicates, is received and, for each encrypted entity, a corresponding set of entity ciphertexts is generated based on an initial embedding of entity features. for each encrypted predicate, a corresponding predicate ciphertext is generated based on an initial embedding of predicate features. a machine learning process is iteratively executed, on the sets of entity ciphertexts and the predicate ciphertexts, to update embeddings of the entity features of the encrypted entities and update embeddings of predicate features of the encrypted predicates, to generate a computer model for embedding entities and predicates. a final embedding is output based on the updated embeddings of the entity features and predicate features of the computer model.
Inventor(s): Leonid Rodniansky of Allston MA (US) for international business machines corporation, Tania Butovsky of Needham MA (US) for international business machines corporation, Mikhail Shpak of New York NY (US) for international business machines corporation
IPC Code(s): H04L9/40, H04L67/02
Abstract: an approach is disclosed for processing one or more http requests and responses, by a protection solution, where a version of the plurality of http requests and responses is at least version 2. when an http settings request is detected in the one or more http requests, by the protection solution, a protected dynamic dictionary is allocated in a protected memory area and an allocation of an application dynamic dictionary in application space in an http server is prevented. when an http header request is detected in the one or more http requests, fields of the http header are decompressed into the protected dynamic dictionary, the http header request is updated to form an updated header request based on content in the protected dynamic dictionary, and the updated header request is sent to the http server.
Inventor(s): Paul Llamas Virgen of Guadalajara (MX) for international business machines corporation, Emmanuel Barajas Gonzalez of Fremont CA (US) for international business machines corporation, Humberto Orozco Cervantes of Tonala (MX) for international business machines corporation, Shaun E. Harrington of Sahuarita AZ (US) for international business machines corporation
IPC Code(s): H04N21/84, G06F3/01, H04N21/44
Abstract: multimedia stream enhancement includes automatically analyzing a multimedia stream and identifying items of interest therein, building metadata, about the stream, that describes the identified items of interest and includes indications of each item of interest and a respective location of that item of interest, providing, by a stream producer device, the stream and the metadata to stream consumer devices, receiving feedback from at least one stream consumer device as the stream producer device provides the stream to the at least one stream consumer device, and using the feedback to generate updated metadata about the stream for provision to one or more stream consumer devices of the stream consumer devices.
Inventor(s): Arthur J. Higby of Cottekill NY (US) for international business machines corporation, DAVID CLIFFORD LONG of WAPPINGERS FALLS NY (US) for international business machines corporation, James Busby of New Paltz NY (US) for international business machines corporation, William Santiago-Fernandez of Hopewell Junction NY (US) for international business machines corporation, John R. Dangler of Rochester MN (US) for international business machines corporation, Russell A. Budd of North Salem NY (US) for international business machines corporation, Philipp K Buchling Rego of Wappingers Falls NY (US) for international business machines corporation, Hannah Wendling of Poughquag NY (US) for international business machines corporation, Lauren Boston of Poughkeepsie NY (US) for international business machines corporation
IPC Code(s): H05K1/02, H05K5/02
Abstract: a structure of a circuitry substrate for securing an area from tampering is disclosed. the structure includes a circuitry substrate with at least one of a top tamper enclosure and a bottom tamper enclosure covering a component in a protected area of the circuitry substrate. the top and bottom tamper enclosures are adhesively bonded to a surface of the circuitry substrate, and a tear initiation site is added to a side of the perimeter of circuitry substrate bordering the protected area that includes at least one tamper enclosure, such that the tear initiation site is located and configured to enable propagation of a delamination of at least one internal layer of the circuitry substrate and a severing of a security circuit when a removal force is applied to the at least one of the top tamper enclosure and the bottom tamper enclosure.
Inventor(s): Gen Tsutsui of Glenmont NY (US) for international business machines corporation, Shogo Mochizuki of Mechanicville NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L27/11
Abstract: a semiconductor structure is presented including a bottom field effect transistor (fet) including a plurality of bottom source/drain (s/d) epi regions, a top fet including a plurality of top s/d epi regions, a bonding dielectric layer disposed directly between the bottom fet and the top fet, and a node contact advantageously extending from a bottom s/d epi region of the plurality of bottom s/d epi regions of the bottom fet through the bonding dielectric layer and into the top fet. the bottom fet includes an inverter gate. the top fet electrically connects to back-end-of-line (beol) components and the bottom fet electrically connects to a backside power delivery network (bspdn).
Inventor(s): Jens Künzer of Boeblingen (DE) for international business machines corporation, Tobias Werner of Weil Im Schoenbuch (DE) for international business machines corporation, Iris Maria Leefken of Dettenhausen (DE) for international business machines corporation, Gerhard Hellner of Boeblingen (DE) for international business machines corporation
IPC Code(s): H10B10/00
Abstract: a processor may form a first power line and a second power line. the processor may form a first memory cell with at least six transistors and a second memory cell with at least six transistors. the first pair of transistors of the first memory cell may be stacked vertically and connected at a common net. the common net may be arranged transverse to the first pair of transistors. the first pair of transistors may be configured to share the first power line. the second pair of transistors of the first memory cell may be stacked vertically and connected at a common net. the common net may be arranged transverse to the second pair of transistors. the second pair of transistors may be configured to share the second power line. the transistors of the first pair of transistors are configured to operate independently from the second pair of transistors.
Inventor(s): Julien Frougier of Albany NY (US) for international business machines corporation, Kangguo Cheng of Schenectady NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Min Gyu Sung of Latham NY (US) for international business machines corporation
IPC Code(s): H01L27/11507
Abstract: a memory device includes a substrate and vertically stacked ferroelectric capacitors formed on the substrate. a first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a constant voltage is applied. first and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors. in some instances, a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. the different thicknesses allow the capacitive output for each capacitor to produce different electric field outputs. accordingly, a combination of different output signals can be produced based on different threshold voltage levels for each capacitor contributing to the output.
Inventor(s): Alexander Reznicek of Troy NY (US) for international business machines corporation, Young-Suk Choi of Niskayuna NY (US) for international business machines corporation, Matthias Georg Gottwald of Ridgefield CT (US) for international business machines corporation, Daniel P. Morris of Purchase NY (US) for international business machines corporation
IPC Code(s): H01L43/02, H01L27/22, H01L43/12
Abstract: one or more magnetic tunneling junction (mtj) pillars are disposed on a substrate. the pillars have one or more magnetic reference layers and one or more magnetic free layers. the magnetic free layers have one or more external surfaces and are made of a magnetic free layer material containing atomic percentage amount of boron. a boron-containing encapsulation layer encapsulates the mtj pillar(s) and is in direct contact with the magnetic free layer external surfaces. the boron-containing encapsulation layer contains an atomic percentage amount of boron greater than the magnetic free layer atomic percentage amount of boron. embodiments of the boron-containing encapsulation layer contain at least 95 percent pure boron and are between 1 and 3 nanometers thick. accordingly, the boron-containing encapsulation layer controls and limits the amount of boron diffusing out of the magnetic free layer across a boron diffusion interface formed between the magnetic free layer external surfaces and the boron-containing encapsulation layer. alternative embodiments of boron-containing encapsulation layers and methods of making mtj devices are disclosed.
International Business Machines Corporation patent applications on April 11th, 2024
- International Business Machines Corporation
- G06F3/06
- International business machines corporation
- G06F11/34
- G06F9/455
- G06F12/0802
- G06F13/16
- G06F13/40
- G06F13/42
- G06F16/23
- G06F16/27
- G06F16/338
- G06F40/20
- G06F16/901
- G06F16/906
- G06F16/9032
- G06F16/93
- G06F17/18
- G06Q10/04
- G06F21/52
- G06N20/00
- G06F21/56
- G06F21/60
- G06F30/31
- G06F30/398
- G06F40/51
- G06F40/44
- G06N3/04
- G06N3/08
- G06N3/092
- G06N7/08
- G06F9/38
- G06F9/50
- G06F15/16
- G06F17/11
- G06N10/00
- G06N10/20
- G06N10/40
- G06K9/62
- G06Q10/06
- G06Q30/0282
- G06Q30/02
- G06Q50/02
- G06V20/10
- G06V20/13
- G06T5/20
- G06T17/00
- G06T7/00
- G06T7/11
- G01M99/00
- G06T7/60
- G06T11/60
- G09B19/06
- G09B5/06
- G10L13/08
- G10L25/18
- G11C11/42
- G11C11/56
- G11C15/04
- H01L23/48
- H01L21/8234
- H01L27/088
- H01L29/06
- H01L29/08
- H01L29/66
- H01L29/775
- H01L29/786
- H01L23/522
- H01L21/306
- H01L21/3205
- H01L23/528
- H01L49/02
- H01L29/417
- H01L29/423
- H01S5/024
- H01L23/367
- H01L23/373
- H04B15/00
- H04L7/00
- H04L9/00
- H04L9/40
- H04L67/02
- H04N21/84
- G06F3/01
- H04N21/44
- H05K1/02
- H05K5/02
- H01L27/11
- H10B10/00
- H01L27/11507
- H01L43/02
- H01L27/22
- H01L43/12
