Intel corporation (20240128205). HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS simplified abstract
Contents
- 1 HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS
Organization Name
Inventor(s)
Debendra Mallik of Chandler AZ (US)
Ravindranath Mahajan of Chandler AZ (US)
Robert Sankman of Phoenix AZ (US)
Shawna Liff of Scottsdale AZ (US)
Srinivas Pietambaram of Chandler AZ (US)
Bharat Penmecha of Phoenix AZ (US)
HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240128205 titled 'HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS
Simplified Explanation
The abstract describes electronic packages with nested components and methods of fabricating them. Here is a simplified explanation of the abstract:
- Electronic packages with nested components are disclosed.
- The package includes an interposer with a cavity for the nested component.
- A die is connected to the interposer and the nested component with interconnects.
- The interconnects consist of bumps, bump pads, and additional bumps.
Potential Applications
The technology described in this patent application could be applied in various electronic devices such as smartphones, tablets, laptops, and other portable electronic devices.
Problems Solved
This technology solves the problem of efficiently integrating nested components within electronic packages, allowing for compact and reliable electronic devices.
Benefits
The benefits of this technology include improved space utilization, enhanced performance, and increased reliability of electronic packages.
Potential Commercial Applications
The technology could find applications in the consumer electronics industry, semiconductor manufacturing, and other industries requiring compact and reliable electronic packaging solutions.
Possible Prior Art
One possible prior art could be the use of stacked die technology in electronic packaging to achieve compact designs. However, the specific configuration of nested components within a cavity in an interposer as described in this patent application may be novel.
Unanswered Questions
How does this technology compare to existing methods of integrating components in electronic packages?
This article does not provide a direct comparison with existing methods of integrating components in electronic packages. Further research or a comparative analysis would be needed to answer this question.
What are the potential challenges in implementing this technology on a large scale in manufacturing processes?
The article does not address the potential challenges in implementing this technology on a large scale in manufacturing processes. Factors such as cost, scalability, and compatibility with existing manufacturing equipment could be significant challenges that need to be explored further.
Original Abstract Submitted
embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. in an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. in an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. in an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
