Intel corporation (20240128181). PACKAGE SUBSTRATE WITH DUAL DAMASCENE BASED SELF-ALIGNED VIAS simplified abstract
Contents
- 1 PACKAGE SUBSTRATE WITH DUAL DAMASCENE BASED SELF-ALIGNED VIAS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 PACKAGE SUBSTRATE WITH DUAL DAMASCENE BASED SELF-ALIGNED VIAS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
PACKAGE SUBSTRATE WITH DUAL DAMASCENE BASED SELF-ALIGNED VIAS
Organization Name
Inventor(s)
Jeremy Ecton of Gilbert AZ (US)
Brandon C. Marin of Gilbert AZ (US)
Srinivas V. Pietambaram of Chandler AZ (US)
Hiroki Tanaka of Gilbert AZ (US)
Haobo Chen of Chandler AZ (US)
PACKAGE SUBSTRATE WITH DUAL DAMASCENE BASED SELF-ALIGNED VIAS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240128181 titled 'PACKAGE SUBSTRATE WITH DUAL DAMASCENE BASED SELF-ALIGNED VIAS
Simplified Explanation
The microelectronic assembly described in the abstract includes a package substrate with multiple layers of organic dielectric material and conductive traces, as well as integrated circuit dies coupled to one side of the substrate. The layers of organic dielectric material alternate with conductive vias, with some layers containing both a conductive via and a conductive trace not coplanar with each other. The conductive via's sidewalls are orthogonal to the conductive trace, and protrude from the edges of the trace by a small amount.
- Package substrate with multiple layers of organic dielectric material and conductive traces
- Integrated circuit dies coupled to one side of the substrate
- Layers of organic dielectric material alternate with conductive vias
- Some layers contain both a conductive via and a conductive trace not coplanar with each other
- Conductive via's sidewalls are orthogonal to the conductive trace
- Sidewalls of the conductive via protrude from the edges of the trace by a small amount
Potential Applications
This technology could be used in various microelectronic devices such as smartphones, tablets, and other portable electronic devices.
Problems Solved
This technology helps in improving the performance and reliability of microelectronic assemblies by providing efficient interconnects between different components.
Benefits
The benefits of this technology include enhanced electrical connectivity, reduced signal interference, and improved overall functionality of microelectronic devices.
Potential Commercial Applications
Potential commercial applications of this technology include the semiconductor industry, consumer electronics manufacturers, and companies involved in the production of advanced electronic devices.
Possible Prior Art
One possible prior art could be the use of traditional PCBs with simpler interconnect structures compared to the advanced design described in the patent application.
Unanswered Questions
How does this technology compare to existing interconnect solutions in terms of cost-effectiveness?
The article does not provide information on the cost implications of implementing this technology compared to traditional interconnect solutions.
What are the potential challenges in scaling up the production of microelectronic assemblies using this technology?
The article does not address the scalability issues or potential challenges that may arise when mass-producing microelectronic assemblies with this innovative design.
Original Abstract Submitted
embodiments of a microelectronic assembly that includes: a package substrate comprising a plurality of layers of organic dielectric material and conductive traces alternating with conductive vias in alternate layers of the organic dielectric material; and a plurality of integrated circuit dies coupled to a first side of the package substrate by interconnects, in which: the plurality of layers of the organic dielectric material comprises at least a first layer having a conductive via and a second layer having a conductive trace in contact with the conductive via, the second layer is not coplanar with the first layer, sidewalls of the conductive via are orthogonal to the conductive trace, and two opposing sidewalls of the conductive via separated by a width of the conductive via protrude from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via.
