TECHNOLOGIES FOR ATOMIC LAYER DEPOSITION FOR FERROELECTRIC TRANSISTORS

The patent application describes technologies for a field effect transistor (FET) with a ferroelectric gate dielectric. Here are the key points of the innovation:

Perovskite stack grown on a buffer layer as part of manufacturing a transistor
Doped semiconductor layers alternating with lattice-matched layers in the perovskite stack
Etching away lattice-matched layers to leave doped semiconductor layers as fins for a ribbon FET
Conformally growing a ferroelectric layer on the fins for high-quality ferroelectric layers above and below the fins
Growing a gate on the ferroelectric layer

Potential Applications

The technology can be applied in the development of high-performance field effect transistors with ferroelectric gate dielectrics for various electronic devices.

Problems Solved

1. Enhancing the quality of doped semiconductor layers in FETs 2. Improving the performance and efficiency of electronic devices by utilizing ferroelectric gate dielectrics

Benefits

1. Increased efficiency and speed of electronic devices 2. Enhanced reliability and stability of FETs 3. Potential for miniaturization and integration in semiconductor devices

Potential Commercial Applications

The technology can find applications in the semiconductor industry for the production of advanced electronic devices such as smartphones, computers, and sensors.

Possible Prior Art

Prior art in the field of ferroelectric gate dielectrics for FETs may include research papers, patents, or products utilizing similar technologies.

Unanswered Questions

How does this technology compare to existing FET designs with traditional gate dielectrics?

The article does not provide a direct comparison between this technology and existing FET designs with traditional gate dielectrics. It would be interesting to know the specific performance differences and advantages of using a ferroelectric gate dielectric in FETs.

What are the potential challenges in scaling up the manufacturing process of FETs with ferroelectric gate dielectrics?

The article does not address the scalability of the manufacturing process for FETs with ferroelectric gate dielectrics. Understanding the challenges and limitations in large-scale production could be crucial for the commercial viability of this technology.

Original Abstract Submitted

technologies for a field effect transistor (fet) with a ferroelectric gate dielectric are disclosed. in an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. the perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. the lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon fet. a ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. a gate can then be grown on the ferroelectric layer.

Intel corporation (20240120415). TECHNOLOGIES FOR ATOMIC LAYER DEPOSITION FOR FERROELECTRIC TRANSISTORS simplified abstract

Contents

TECHNOLOGIES FOR ATOMIC LAYER DEPOSITION FOR FERROELECTRIC TRANSISTORS

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