Intel corporation (20240113073). SIDE OF A DIE THAT IS COPLANAR WITH A SIDE OF A MOLDING simplified abstract
Contents
- 1 SIDE OF A DIE THAT IS COPLANAR WITH A SIDE OF A MOLDING
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SIDE OF A DIE THAT IS COPLANAR WITH A SIDE OF A MOLDING - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SIDE OF A DIE THAT IS COPLANAR WITH A SIDE OF A MOLDING
Organization Name
Inventor(s)
Xavier F. Brun of Chandler AZ (US)
Trianggono Widodo of Hillsboro OR (US)
SIDE OF A DIE THAT IS COPLANAR WITH A SIDE OF A MOLDING - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240113073 titled 'SIDE OF A DIE THAT IS COPLANAR WITH A SIDE OF A MOLDING
Simplified Explanation
The abstract describes a patent application related to creating a package with a die embedded in a molding, where the surfaces of the die and molding are coplanar. The die is initially finished on one side and unfinished on the other, and during package manufacture, molding is placed around the die and planarized to reveal TSVs for electrical coupling.
- Die embedded in molding with coplanar surfaces:
- Involves embedding a die in a molding where the surfaces are aligned.
- Planarization process:
- After molding is placed around the die, planarization is done to reveal TSVs for electrical coupling.
- TSVs for electrical coupling:
- Through planarization, one or more TSVs are exposed for connecting the die to other components.
Potential Applications
This technology could be applied in semiconductor packaging, microelectronics, and integrated circuit manufacturing.
Problems Solved
This innovation solves the challenge of integrating a die into a package with coplanar surfaces and enabling electrical coupling through TSVs.
Benefits
The benefits of this technology include improved electrical connectivity, compact packaging, and enhanced performance of electronic devices.
Potential Commercial Applications
Potential commercial applications of this technology include consumer electronics, automotive electronics, and telecommunications equipment.
Possible Prior Art
One possible prior art could be the use of flip chip technology in semiconductor packaging to achieve electrical connections.
Unanswered Questions
How does the planarization process impact the overall cost of package manufacture?
The cost implications of the planarization process in terms of equipment, time, and materials used need further exploration.
What are the potential challenges in scaling up this technology for mass production?
The scalability of this technology for large-scale production and any associated challenges require further investigation.
Original Abstract Submitted
embodiments herein relate to systems, apparatuses, or processes creating a package that includes a die embedded in a molding, where a surface of the die is coplanar with a surface of the molding. during a stage of package manufacture, the die may have a finished side that may be coupled with a component of the package, and an unfinished side. during a subsequent stage of package manufacture, molding may be placed around the die, and then the molding and at least a portion of the die may be planarized, which may involve grinding and polishing. the planarization may reveal one or more tsv at the side of the die which is now finished and ready for electrical coupling with other components. as a result, a side of the molding at a side of the die to be coplanar. other embodiments may be described and/or claimed.
