Intel corporation (20240113007). AIR GAP ARCHITECTURE FOR HIGH SPEED I/O SUBSTRATE TRACES simplified abstract

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AIR GAP ARCHITECTURE FOR HIGH SPEED I/O SUBSTRATE TRACES

Organization Name

intel corporation

Inventor(s)

Benjamin Duong of Phoenix AZ (US)

Kristof Darmawikarta of Chandler AZ (US)

Srinivas Pietambaram of Chandler AZ (US)

AIR GAP ARCHITECTURE FOR HIGH SPEED I/O SUBSTRATE TRACES - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240113007 titled 'AIR GAP ARCHITECTURE FOR HIGH SPEED I/O SUBSTRATE TRACES

Simplified Explanation

The abstract describes a microelectronic integrated circuit package structure with two substrates having bond plane structures in direct physical contact. A conductive trace on the first substrate is adjacent to a bonding interface between the bond plane structures, with air gaps present to prevent short circuits.

  • The patent application describes a microelectronic integrated circuit package structure with two substrates and bond plane structures in direct contact.
  • A conductive trace on the first substrate is positioned near the bonding interface between the bond plane structures, with air gaps to prevent short circuits.

Potential Applications

The technology described in this patent application could be used in various microelectronic devices such as smartphones, tablets, and computers.

Problems Solved

This technology helps prevent short circuits in microelectronic integrated circuit package structures, improving the reliability and performance of electronic devices.

Benefits

The use of air gaps in the design helps enhance the overall functionality and longevity of microelectronic integrated circuit package structures.

Potential Commercial Applications

The technology could be applied in the manufacturing of consumer electronics, industrial equipment, and automotive systems.

Possible Prior Art

One possible prior art could be the use of insulating materials to prevent short circuits in microelectronic devices.

Unanswered Questions

How does the technology impact the overall size of the microelectronic integrated circuit package structure?

The abstract does not provide information on whether the technology affects the size of the package structure.

What materials are used in the construction of the substrates and bond plane structures?

The abstract does not specify the materials used in the construction of the substrates and bond plane structures.


Original Abstract Submitted

microelectronic integrated circuit package structures include a first substrate comprising a first bond plane structure on a surface of the first substrate, and a second substrate comprising a second bond plane structure on a surface of the second substrate, where the first and second bond plane structures are in direct physical contact. a conductive trace on the surface of the first substrate is adjacent to a bonding interface between the first and second bond plane structures and over a recessed surface of the first substrate. a first air gap is between the conductive trace and the recessed surface of the first substrate and a second air gap is between the conductive trace and the bonding interface.