Intel corporation (20240111826). HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT simplified abstract

HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT

Organization Name

intel corporation

Inventor(s)

Jiasheng Chen of El Dorado Hills CA (US)

Kevin Hurd of Flagler Beach FL (US)

Changwon Rhee of Rocklin CA (US)

Jorge Parra of El Dorado Hills CA (US)

Fangwen Fu of Folsom CA (US)

Theo Drane of El Dorado Hills CA (US)

William Zorn of Woodinville WA (US)

Peter Caday of Hillsboro OR (US)

Gregory Henry of Hillsboro OR (US)

Guei-Yuan Lueh of San Jose CA (US)

Farzad Chehrazi of Hillsboro OR (US)

Amit Karande of Hillsboro OR (US)

Turbo Majumder of Portland OR (US)

Xinmin Tian of Union City CA (US)

Milind Girkar of Hillsboro OR (US)

Hong Jiang of Los Altos CA (US)

HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240111826 titled 'HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT

Simplified Explanation

The apparatus disclosed in the patent application is designed to facilitate hardware enhancements for double precision systolic support. It includes matrix acceleration hardware with double-precision matrix multiplication circuitry, adders, an accumulator circuit, and a down conversion and rounding circuit.

• Matrix acceleration hardware with double-precision matrix multiplication circuitry
• Multiplier circuits to multiply pairs of input source operands in a double-precision floating-point format
• Adders to accumulate the multiplier outputs in a high precision intermediate format
• Accumulator circuit to generate an accumulator output in the high precision intermediate format
• Down conversion and rounding circuit to produce the final result in the double-precision floating-point format

---

1. 1. 1. Potential Applications

This technology can be applied in high-performance computing systems, scientific simulations, and machine learning algorithms that require double-precision calculations.

1. 1. 1. Problems Solved

This innovation solves the problem of efficiently performing double-precision matrix multiplication operations in hardware, improving the speed and accuracy of computations.

1. 1. 1. Benefits

The benefits of this technology include faster processing of double-precision calculations, increased accuracy in numerical computations, and enhanced performance in applications requiring high precision.

1. 1. 1. Potential Commercial Applications

Potential commercial applications of this technology include supercomputers, data centers, artificial intelligence systems, and scientific research facilities.

1. 1. 1. Possible Prior Art

One possible prior art for this technology could be existing hardware accelerators for single-precision matrix multiplication operations. However, the specific implementation of double-precision systolic support as described in the patent application may be a novel advancement in the field.

---

1. 1. 1. 1. Unanswered Questions

1. 1. 1. How does this technology compare to existing double-precision matrix multiplication hardware accelerators?

This article does not provide a direct comparison with existing double-precision matrix multiplication hardware accelerators. It would be helpful to understand the specific advantages and differences of this apparatus compared to current solutions.

1. 1. 1. What impact could this technology have on the performance of deep learning algorithms in neural networks?

The article does not address the potential impact of this technology on the performance of deep learning algorithms in neural networks. It would be interesting to explore how the enhanced double-precision support could improve the training and inference speed of complex neural network models.

Original Abstract Submitted

an apparatus to facilitate hardware enhancements for double precision systolic support is disclosed. the apparatus includes matrix acceleration hardware having double-precision (dp) matrix multiplication circuitry including a multiplier circuits to multiply pairs of input source operands in a dp floating-point format; adders to receive multiplier outputs from the multiplier circuits and accumulate the multiplier outputs in a high precision intermediate format; an accumulator circuit to accumulate adder outputs from the adders with at least one of a third global source operand on a first pass of the dp matrix multiplication circuitry or an intermediate result from the first pass on a second pass of the dp matrix multiplication circuitry, wherein the accumulator circuit to generate an accumulator output in the high precision intermediate format; and a down conversion and rounding circuit to down convert and round an output of the second pass as final result in the dp floating-point format.