Intel corporation (20240105801). INTEGRATED CIRCUIT STRUCTURES WITH GATE VOLUME REDUCTION simplified abstract
Contents
- 1 INTEGRATED CIRCUIT STRUCTURES WITH GATE VOLUME REDUCTION
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 INTEGRATED CIRCUIT STRUCTURES WITH GATE VOLUME REDUCTION - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
INTEGRATED CIRCUIT STRUCTURES WITH GATE VOLUME REDUCTION
Organization Name
Inventor(s)
Leonard P. Guler of Hillsboro OR (US)
Sukru Yemenicioglu of Portland OR (US)
Raghuram Gandikota of Portland OR (US)
Krishna Ganesan of Portland OR (US)
Sean Pursel of Hillsboro OR (US)
INTEGRATED CIRCUIT STRUCTURES WITH GATE VOLUME REDUCTION - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240105801 titled 'INTEGRATED CIRCUIT STRUCTURES WITH GATE VOLUME REDUCTION
Simplified Explanation
The patent application describes integrated circuit structures with gate volume reduction. A simplified explanation of the abstract is that the structure includes a sub-fin structure beneath a stack of nanowires, with a dielectric backbone structure and gate electrode on opposite sides of the nanowire stack.
- Sub-fin structure beneath a stack of nanowires
- Dielectric backbone structure along one side of the nanowire stack
- Gate electrode on the other side of the nanowire stack
- Gate dielectric structure between the gate electrode and nanowire stack
Potential Applications
The technology could be applied in the development of advanced integrated circuits for various electronic devices, such as smartphones, computers, and IoT devices.
Problems Solved
This technology helps reduce the gate volume in integrated circuit structures, leading to improved performance and efficiency in electronic devices.
Benefits
The gate volume reduction can result in enhanced speed, power efficiency, and overall performance of integrated circuits.
Potential Commercial Applications
Potential commercial applications include semiconductor manufacturing companies looking to enhance the performance of their electronic products through advanced integrated circuit structures.
Possible Prior Art
One possible prior art could be the use of similar gate volume reduction techniques in the fabrication of integrated circuits, although specific details may vary.
Unanswered Questions
How does the gate volume reduction impact the overall size of the integrated circuit structure?
The article does not provide information on whether the gate volume reduction technique affects the overall size of the integrated circuit structure.
What are the specific materials used in the fabrication of the sub-fin structure and nanowires?
The article does not detail the specific materials used in the fabrication process of the sub-fin structure and nanowires.
Original Abstract Submitted
integrated circuit structures having gate volume reduction, and methods of fabricating integrated circuit structures having gate volume reduction, are described. for example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires, the stack of nanowires having a first side and a second side. a dielectric backbone structure is along the first side of the stack of nanowires. the dielectric backbone structure has a bottom above a bottom of the sub-fin. a gate electrode is over the stack of nanowires and is along the second side of the stack of nanowires. a gate dielectric structure is between the gate electrode and the stack of nanowires.
