Intel corporation (20240105575). ELECTROLYTIC SURFACE FINISH ARCHITECTURE simplified abstract

ELECTROLYTIC SURFACE FINISH ARCHITECTURE

Organization Name

intel corporation

Inventor(s)

Jason M. Gamba of Gilbert AZ (US)

Haifa Hariri of Phoenix AZ (US)

Kristof Darmawikarta of Chandler AZ (US)

Srinivas V. Pietambaram of Chandler AZ (US)

Hiroki Tanaka of Gilbert AZ (US)

Kyle Mcelhinny of Tempe AZ (US)

Xiaoying Guo of Chandler AZ (US)

Steve S. Cho of Chandler AZ (US)

Ali Lehaf of Phoenix AZ (US)

Haobo Chen of Gilbert AZ (US)

Bai Nie of Chandler AZ (US)

Numair Ahmed of Chandler AZ (US)

ELECTROLYTIC SURFACE FINISH ARCHITECTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240105575 titled 'ELECTROLYTIC SURFACE FINISH ARCHITECTURE

Simplified Explanation

The patent application abstract describes a package substrate with specific dimensions for the pad, surface finish, and solder resist.

• The package substrate includes a core with a pad on top, where the pad has a certain width.
• A surface finish is applied over the pad with a width that matches the pad's width.
• A solder resist is then added over the pad, with an opening exposing part of the surface finish.
• The opening in the solder resist is narrower than the width of the surface finish.

Potential Applications

This technology could be applied in the manufacturing of electronic devices, such as integrated circuits, where precise dimensions and materials are crucial for performance.

Problems Solved

This technology helps in ensuring proper connectivity and protection of the components on the package substrate by controlling the dimensions and materials used in the construction.

Benefits

The precise matching of widths between the pad, surface finish, and solder resist helps in maintaining the integrity and reliability of the package substrate in electronic applications.

Potential Commercial Applications

One potential commercial application of this technology could be in the production of advanced electronic devices for industries like telecommunications, automotive, and consumer electronics.

Possible Prior Art

Prior art may include existing methods of forming package substrates with different dimensions and materials for the pad, surface finish, and solder resist.

How does this technology compare to existing package substrate designs in terms of performance and reliability?

This article does not provide a direct comparison with existing package substrate designs to evaluate the performance and reliability differences.

What are the specific electronic devices or industries that could benefit the most from this technology?

The article does not specify the targeted electronic devices or industries that could see the most significant advantages from implementing this technology.

Original Abstract Submitted

embodiments disclosed herein include package substrates and methods of forming package substrates. in an embodiment, the package substrate comprises a core, and a pad over the core, where the pad has a first width. in an embodiment, a surface finish is over the pad, where the surface finish has a second width that is substantially equal to the first width. in an embodiment, the package substrate further comprises a solder resist over the pad, where the solder resist comprises an opening that exposes a portion of the surface finish. in an embodiment, the opening has a third width that is smaller than the second width.