|
|
| Line 1: |
Line 1: |
| − | '''Summary of the patent applications from Intel Corporation on November 30th, 2023'''
| + | ==Patent applications for intel on November 30th, 2023== |
| − | | |
| − | Intel Corporation has recently filed several patents related to various aspects of technology. These patents cover areas such as layer 1 (L1)/layer 2 (L2) triggered mobility (LTM) aspects, electronic device display interfaces for camera control, network interface devices with direct memory access (DMA) circuitry, secure connections over Remote Direct Memory Access (RDMA), software-based management of the physical layer (PHY) of a link, adapting secure sounding signals in communication devices, implementing high-speed Ethernet links using a hybrid PHY, gate-all-around integrated circuit structures with tightly spaced nanowires, and thin film transistors with double gates.
| |
| − | | |
| − | Notable applications of these patents include:
| |
| − | * Layer 1 (L1)/layer 2 (L2) triggered mobility (LTM) aspects, including inter-cell mobility, split architectures, dynamic cell group changes, activation, and deactivation.
| |
| − | * Electronic device display interfaces for controlling a camera and reviewing captured images, providing a simplified and user-friendly interface.
| |
| − | * Network interface devices with direct memory access (DMA) circuitry for processing packets and determining Extended Sequence Number (ESN) values.
| |
| − | * Secure connections over Remote Direct Memory Access (RDMA) with two network interface devices, acting as endpoints for Transport Layer Security (TLS) over RDMA connections.
| |
| − | * Software-based application for managing the physical layer (PHY) of a link using an application programming interface (API) to configure the physical layer through firmware.
| |
| − | * Adapting secure sounding signals in communication devices based on negotiated bandwidth for secure communication.
| |
| − | * Implementing high-speed Ethernet links using a hybrid PHY with non-interleaved or interleaved RS-FEC sublayers, determined during link training.
| |
| − | * Gate-all-around integrated circuit structures with tightly spaced nanowires and methods for fabricating them.
| |
| − | * Thin film transistors with double gates for improved control and performance.
| |
| − | | |
| − | In summary, Intel Corporation has filed patents covering a wide range of technological advancements, including mobility aspects, camera control interfaces, network interface devices, secure connections, software-based management of the physical layer, adaptive sounding signals, high-speed Ethernet links, integrated circuit structures, and thin film transistors. These patents demonstrate Intel's commitment to innovation and advancing technology in various fields.
| |
| − | | |
| − | | |
| − | | |
| − | | |
| − | ==Patent applications for Intel Corporation on November 30th, 2023== | |
| − | | |
| − | ===SOCKETED MEMORY ARCHITECTURE PACKAGE AND METHOD ([[US Patent Application 17825558. SOCKETED MEMORY ARCHITECTURE PACKAGE AND METHOD simplified abstract (Intel Corporation)|17825558]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Siva Prasad Jangili Ganga
| |
| − | | |
| − | | |
| − | ===SYSTEMS AND METHODS FOR COMPUTING DOT PRODUCTS OF NIBBLES IN TWO TILE OPERANDS ([[US Patent Application 18449651. SYSTEMS AND METHODS FOR COMPUTING DOT PRODUCTS OF NIBBLES IN TWO TILE OPERANDS simplified abstract (Intel Corporation)|18449651]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Raanan Sade
| |
| − | | |
| − | | |
| − | ===BOOT PROCESS FOR EARLY DISPLAY INITIALIZATION AND VISUALIZATION ([[US Patent Application 18361128. BOOT PROCESS FOR EARLY DISPLAY INITIALIZATION AND VISUALIZATION simplified abstract (Intel Corporation)|18361128]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Subrata Banik
| |
| − | | |
| − | | |
| − | ===SYSTEMS AND METHODS FOR IMPLEMENTING AN INTELLIGENT APPLICATION PROGRAM INTERFACE FOR AN INTELLIGENT OPTIMIZATION PLATFORM ([[US Patent Application 18326467. SYSTEMS AND METHODS FOR IMPLEMENTING AN INTELLIGENT APPLICATION PROGRAM INTERFACE FOR AN INTELLIGENT OPTIMIZATION PLATFORM simplified abstract (Intel Corporation)|18326467]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Alexandra Johnson
| |
| − | | |
| − | | |
| − | ===POWER ERROR MONITORING AND REPORTING WITHIN A SYSTEM ON CHIP FOR FUNCTIONAL SAFETY ([[US Patent Application 18302999. POWER ERROR MONITORING AND REPORTING WITHIN A SYSTEM ON CHIP FOR FUNCTIONAL SAFETY simplified abstract (Intel Corporation)|18302999]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Prashant D. Chaudhari
| |
| − | | |
| − | | |
| − | ===ACCELERATED MEMORY TRAINING THROUGH IN-BAND CONFIGURATION REGISTER UPDATE MODE ([[US Patent Application 18232765. ACCELERATED MEMORY TRAINING THROUGH IN-BAND CONFIGURATION REGISTER UPDATE MODE simplified abstract (Intel Corporation)|18232765]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Saravanan SETHURAMAN
| |
| − | | |
| − | | |
| − | ===USB TYPE-C SUBSYSTEM ([[US Patent Application 17826933. USB TYPE-C SUBSYSTEM simplified abstract (Intel Corporation)|17826933]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Udaya Natarajan
| |
| − | | |
| − | | |
| − | ===MULTI-PORT MEMORY LINK EXPANDER TO SHARE DATA AMONG HOSTS ([[US Patent Application 18250325. MULTI-PORT MEMORY LINK EXPANDER TO SHARE DATA AMONG HOSTS simplified abstract (Intel Corporation)|18250325]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Zhuangzhi Li
| |
| − | | |
| − | | |
| − | ===AI-BASED COMPONENT PLACEMENT TECHNOLOGY FOR PCB CIRCUITS ([[US Patent Application 18326772. AI-BASED COMPONENT PLACEMENT TECHNOLOGY FOR PCB CIRCUITS simplified abstract (Intel Corporation)|18326772]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Jianfang Zhu
| |
| − | | |
| − | | |
| − | ===MISUSE INDEX FOR EXPLAINABLE ARTIFICIAL INTELLIGENCE IN COMPUTING ENVIRONMENTS ([[US Patent Application 18323843. MISUSE INDEX FOR EXPLAINABLE ARTIFICIAL INTELLIGENCE IN COMPUTING ENVIRONMENTS simplified abstract (Intel Corporation)|18323843]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | GLEN J. ANDERSON
| |
| − | | |
| − | | |
| − | ===NEURAL NETWORK TRAINING AND INFERENCE WITH HIERARCHICAL ADJACENCY MATRIX ([[US Patent Application 18325348. NEURAL NETWORK TRAINING AND INFERENCE WITH HIERARCHICAL ADJACENCY MATRIX simplified abstract (Intel Corporation)|18325348]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Emmanouil Ioannis Farsarakis
| |
| − | | |
| − | | |
| − | ===APPARATUS AND METHOD FOR SCALABLE QUBIT ADDRESSING ([[US Patent Application 18231917. APPARATUS AND METHOD FOR SCALABLE QUBIT ADDRESSING simplified abstract (Intel Corporation)|18231917]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Xiang ZOU
| |
| − | | |
| − | | |
| − | ===LOSSY COMPRESSION TECHNOLOGY FOR SMALL IMAGE TILES ([[US Patent Application 17824372. LOSSY COMPRESSION TECHNOLOGY FOR SMALL IMAGE TILES simplified abstract (Intel Corporation)|17824372]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Sreenivas Kothandaraman
| |
| − | | |
| − | | |
| − | ===INCREMENTAL 2D-TO-3D POSE LIFTING FOR FAST AND ACCURATE HUMAN POSE ESTIMATION ([[US Patent Application 18031564. INCREMENTAL 2D-TO-3D POSE LIFTING FOR FAST AND ACCURATE HUMAN POSE ESTIMATION simplified abstract (Intel Corporation)|18031564]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Anbang YAO
| |
| − | | |
| − | | |
| − | ===METHOD AND APPARATUS FOR ENCODING BASED ON IMPORTANCE VALUES ([[US Patent Application 18305175. METHOD AND APPARATUS FOR ENCODING BASED ON IMPORTANCE VALUES simplified abstract (Intel Corporation)|18305175]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Yejun Guo
| |
| − | | |
| − | | |
| − | ===FRAGMENT COMPRESSION FOR COARSE PIXEL SHADING ([[US Patent Application 18305511. FRAGMENT COMPRESSION FOR COARSE PIXEL SHADING simplified abstract (Intel Corporation)|18305511]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Prasoonkumar Surti
| |
| − | | |
| − | | |
| − | ===GLARE AND OCCLUDED VIEW COMPENSATION FOR AUTOMOTIVE AND OTHER APPLICATIONS ([[US Patent Application 18322665. GLARE AND OCCLUDED VIEW COMPENSATION FOR AUTOMOTIVE AND OTHER APPLICATIONS simplified abstract (Intel Corporation)|18322665]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Arthur J. Runyan
| |
| − | | |
| − | | |
| − | ===REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION ([[US Patent Application 18213231. REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION simplified abstract (Intel Corporation)|18213231]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Bill NALE
| |
| − | | |
| − | | |
| − | ===VIA STRUCTURE FOR EMBEDDED COMPONENT AND METHOD FOR MAKING SAME ([[US Patent Application 17752941. VIA STRUCTURE FOR EMBEDDED COMPONENT AND METHOD FOR MAKING SAME simplified abstract (Intel Corporation)|17752941]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Kristof Darmawikarta
| |
| − | | |
| − | | |
| − | ===INTEGRATED CIRCUIT ASSEMBLIES HAVING INTERCONNECTION BRIDGES SPANNING INTEGRATED CIRCUIT DEVICES THEREIN ([[US Patent Application 17825340. INTEGRATED CIRCUIT ASSEMBLIES HAVING INTERCONNECTION BRIDGES SPANNING INTEGRATED CIRCUIT DEVICES THEREIN simplified abstract (Intel Corporation)|17825340]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Kai-Chiang Wu
| |
| − | | |
| − | | |
| − | ===INTEGRATED CIRCUIT ASSEMBLIES HAVING INTERCONNECTION BRIDGES SPANNING RETICLE BOUNDARY / DICING STREETS OF MONOLITHIC STRUCTURES THEREIN ([[US Patent Application 17825350. INTEGRATED CIRCUIT ASSEMBLIES HAVING INTERCONNECTION BRIDGES SPANNING RETICLE BOUNDARY / DICING STREETS OF MONOLITHIC STRUCTURES THEREIN simplified abstract (Intel Corporation)|17825350]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Debendra Mallik
| |
| − | | |
| − | | |
| − | ===WRAP-AROUND TRENCH CONTACT STRUCTURE AND METHODS OF FABRICATION ([[US Patent Application 18232670. WRAP-AROUND TRENCH CONTACT STRUCTURE AND METHODS OF FABRICATION simplified abstract (Intel Corporation)|18232670]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Joseph STEIGERWALD
| |
| − | | |
| − | | |
| − | ===THIN FILM TRANSISTORS HAVING DOUBLE GATES ([[US Patent Application 18227233. THIN FILM TRANSISTORS HAVING DOUBLE GATES simplified abstract (Intel Corporation)|18227233]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Abhishek A. SHARMA
| |
| − | | |
| − | | |
| − | ===GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH TIGHT VERTICAL SPACING ([[US Patent Application 18228139. GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH TIGHT VERTICAL SPACING simplified abstract (Intel Corporation)|18228139]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Glenn GLASS
| |
| − | | |
| − | | |
| − | ===ANTENNA SWITCHING FOR IMPROVED IN-DEVICE CO-EXISTENCE PERFORMANCE ([[US Patent Application 18049651. ANTENNA SWITCHING FOR IMPROVED IN-DEVICE CO-EXISTENCE PERFORMANCE simplified abstract (Intel Corporation)|18049651]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Santhosh AP
| |
| − | | |
| − | | |
| − | ===HYBRID PHY WITH INTERLEAVED AND NON-INTERLEAVED RS-FEC AND FEC MODE DETERMINATION DURING ADAPTIVE LINK TRAINING PROTOCOL ([[US Patent Application 18199697. HYBRID PHY WITH INTERLEAVED AND NON-INTERLEAVED RS-FEC AND FEC MODE DETERMINATION DURING ADAPTIVE LINK TRAINING PROTOCOL simplified abstract (Intel Corporation)|18199697]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Kent Lusted
| |
| − | | |
| − | | |
| − | ===ADAPTATION OF SECURE SOUNDING SIGNAL TO BANDWIDTH VARIATION ([[US Patent Application 18190906. ADAPTATION OF SECURE SOUNDING SIGNAL TO BANDWIDTH VARIATION simplified abstract (Intel Corporation)|18190906]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Feng JIANG
| |
| − | | |
| − | | |
| − | ===SOFTWARE-BASED PHYSICAL LAYER CONFIGURATION ([[US Patent Application 18323812. SOFTWARE-BASED PHYSICAL LAYER CONFIGURATION simplified abstract (Intel Corporation)|18323812]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Nishant S. Shah
| |
| − | | |
| − | | |
| − | ===IN-NETWORK COMPUTE OPERATIONS UTILIZING ENCRYPTED COMMUNICATIONS ([[US Patent Application 18230588. IN-NETWORK COMPUTE OPERATIONS UTILIZING ENCRYPTED COMMUNICATIONS simplified abstract (Intel Corporation)|18230588]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Helia A. NAEIMI
| |
| − | | |
| − | | |
| − | ===ENCODING OF AN IMPLICIT PACKET SEQUENCE NUMBER IN A PACKET ([[US Patent Application 18231726. ENCODING OF AN IMPLICIT PACKET SEQUENCE NUMBER IN A PACKET simplified abstract (Intel Corporation)|18231726]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Philip GLYNN
| |
| − | | |
| − | | |
| − | ===USER INTERFACES FOR ELECTRONIC DEVICES ([[US Patent Application 18189789. USER INTERFACES FOR ELECTRONIC DEVICES simplified abstract (Intel Corporation)|18189789]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Peter W. Winer
| |
| − | | |
| − | | |
| − | ===MOBILITY FEATURES FOR NEXT GENERATION CELLULAR NETWORKS ([[US Patent Application 18352810. MOBILITY FEATURES FOR NEXT GENERATION CELLULAR NETWORKS simplified abstract (Intel Corporation)|18352810]])===
| |
| − | | |
| − | | |
| − | '''Main Inventor'''
| |
| − | | |
| − | Yi Guo
| |
