Intel Corporation patent applications published on April 4th, 2024
Summary of the patent applications from Intel Corporation on April 4th, 2024
Intel Corporation has recently filed patents related to memory devices utilizing ferroelectric capacitors, anti-ferroelectric capacitors, and backside integrated circuit capacitor structures. These patents aim to improve data storage, performance, and reliability in electronic devices.
Summary in bullet points:
- Memory devices with ferroelectric capacitors, anti-ferroelectric capacitors, and backside integrated circuit capacitor structures.
- Improved data storage, performance, and reliability in electronic devices.
- Capacitors with layers of hafnium oxide, cerium oxide, and zirconium oxide for enhanced stability.
- Backside integrated circuit capacitor structures with ferroelectric material sandwiched between electrodes.
Notable applications:
- Non-volatile memory systems
- High-performance computing
- Aerospace and defense industries
- Semiconductor manufacturing
- Electronics industry
- Research and development for advanced materials
These patents from Intel Corporation showcase advancements in memory device technology, offering benefits such as improved data retention, faster data access speeds, enhanced security, and lower power consumption. The potential commercial applications span across various industries, highlighting the versatility and innovation of these memory technologies.
Contents
- 1 Patent applications for Intel Corporation on April 4th, 2024
- 1.1 REAL-TIME AUTONOMOUS SEAT ADAPTATION AND IMMERSIVE CONTENT DELIVERY FOR VEHICLES (17956485)
- 1.2 Secure Remote Debugging (17958071)
- 1.3 NANOROD COATING BETWEEN TWO OPTICAL MEDIUMS (17956750)
- 1.4 DIRECTLY COUPLED OPTICAL INTERPOSER (17957341)
- 1.5 PILLAR STRUCTURES ON AN OPTICAL WAVEGUIDE (17956757)
- 1.6 GLASS RECIRCULATOR FOR OPTICAL SIGNAL REROUTING ACROSS PHOTONIC INTEGRATED CIRCUITS (17957094)
- 1.7 HYBRID PLASMONIC WAVEGUIDE AND METHOD FOR HIGH DENSITY PACKAGING INTEGRATED WITH A GLASS INTERPOSER (17957600)
- 1.8 METHOD AND DEVICE FOR FAST, PASSIVE ALIGNMENT IN PHOTONICS ASSEMBLY (18488074)
- 1.9 INTELLIGENT AND ADAPTIVE MULTI-MODAL REAL-TIME SIMULTANEOUS LOCALIZATION AND MAPPING BASED ON LIGHT DETECTION AND RANGING AND CAMERA OR IMAGE SENSORS (17954372)
- 1.10 METHODS AND APPARATUS TO OPERATE CLOSED-LID PORTABLE COMPUTERS (18525248)
- 1.11 CHIP AND PLATFORM LEVEL POWER MONITORING AND SEQUENCING FOR ROBUST STARTUP AND MODE SWITCHING (17957052)
- 1.12 DATA CENTER POWER CONSUMPTION THROUGH MODULATION OF POWER SUPPLY UNIT CONVERSION FREQUENCY (18537740)
- 1.13 CONSTRUCTING HIERARCHICAL CLOCK GATING ARCHITECTURES VIA REWRITING (18538116)
- 1.14 TECHNIQUES TO REDUCE POWER CONSUMPTION FOR A DISTRIBUTED COMPUTATIONAL MODEL MAPPED ONTO A MULTI-PROCESSING NODE SYSTEM (17958108)
- 1.15 STORAGE COMMAND COMPRISING TIME PARAMETER (18532491)
- 1.16 Apparatus, Device, Method and Computer Program for Generating Code using an LLM (18536299)
- 1.17 FREQUENCY SCALING FOR PER-CORE ACCELERATOR ASSIGNMENTS (18369082)
- 1.18 SYSTEMS, METHODS, AND APPARATUS FOR TILE CONFIGURATION (18534012)
- 1.19 DETERMINISTIC BROADCASTING FROM SHARED MEMORY (17957486)
- 1.20 DEVICE, METHOD AND SYSTEM TO DETERMINE A MODE OF PROCESSOR OPERATION BASED ON PAGE TABLE METADATA (17957969)
- 1.21 CIRCUITRY TO PERFORM PARTIAL DECOMPRESSION OPERATIONS (18526910)
- 1.22 ORDERED THREAD DISPATCH FOR THREAD TEAMS (17937270)
- 1.23 SEQUENCING CIRCUIT FOR A PROCESSOR (17957919)
- 1.24 SYNCHRONIZATION UTILIZING LOCAL TEAM BARRIERS FOR THREAD TEAM PROCESSING (17958213)
- 1.25 DYNAMIC APPLICATION PROGRAMMING INTERFACE (API) CONTRACT GENERATION AND CONVERSION THROUGH MICROSERVICE SIDECARS (18541245)
- 1.26 HYBRID PERFORMANCE MONITORING UNIT (PMU) ENUMERATION (18374296)
- 1.27 DEVICE, METHOD, AND SYSTEM TO DETERMINE A COUNT OF RETIRED PREFETCH INSTRUCTIONS (17957978)
- 1.28 HARDWARE PROCESSOR HAVING MULTIPLE MEMORY PREFETCHERS AND MULTIPLE PREFETCH FILTERS (17958334)
- 1.29 TIME-AWARE NETWORK DATA TRANSFER (18532079)
- 1.30 DYNAMIC SWITCHING OF DATA TRANSFERS BETWEEN SIDEBAND AND MAINBAND (18539063)
- 1.31 SINGLE PRECISION SUPPORT FOR SYSTOLIC PIPELINE IN A GRAPHICS ENVIRONMENT (17937229)
- 1.32 HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT (17937252)
- 1.33 ACCURACY-BASED APPROXIMATION OF ACTIVATION FUNCTIONS WITH PROGRAMMABLE LOOK-UP TABLE HAVING AREA BUDGET (18534035)
- 1.34 PROTECTED DATA ACCESSES USING REMOTE COPY OPERATIONS (18370137)
- 1.35 HARDWARE POWER OPTIMIZATION VIA E-GRAPH BASED AUTOMATIC RTL EXPLORATION (18538104)
- 1.36 DEEP LEARNING HARDWARE (18534566)
- 1.37 HARDWARE IP OPTIMIZED CONVOLUTIONAL NEURAL NETWORK (18514069)
- 1.38 3D OBJECT RECOGNITION USING 3D CONVOLUTIONAL NEURAL NETWORK WITH DEPTH BASED MULTI-SCALE FILTERS (18527490)
- 1.39 REAL-TIME SITUATIONAL PLANNING FOR PASSENGER TRANSPORT (17955549)
- 1.40 SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING (17958216)
- 1.41 HUMAN-ROBOT INTERACTIVE WORKSPACE (17957529)
- 1.42 APPARATUS, METHOD, AND COMPUTER-READABLE MEDIUM FOR ROBUST RESPONSE TO ADVERSARIAL PERTURBATIONS USING HYPERDIMENSIONAL VECTORS (18478335)
- 1.43 Scalable Digital Twin Services for intelligent transport systems (ITS) with Optimized Communication and Dynamic Resource Adaptation (17936438)
- 1.44 SELECTIVE FERROELECTRIC DEPLOYMENT FOR SINGLE-TRANSISTOR, MULTIPLE-CAPACITOR DEVICES (17957591)
- 1.45 DEVICE, METHOD AND SYSTEM TO PROVIDE A RANDOM ACCESS MEMORY WITH A FERROELECTRIC RESISTIVE JUNCTION (17957945)
- 1.46 MEMORY ARRAY COMPRISING A FERROELECTRIC DATA STORAGE ELEMENT (17957957)
- 1.47 METAL GATE CUT FORMED AFTER SOURCE AND DRAIN CONTACTS (17936934)
- 1.48 INTEGRATED CIRCUIT INTERCONNECT STRUCTURES WITH NIOBIUM BARRIER MATERIALS (17957721)
- 1.49 INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORES (18535623)
- 1.50 DESIGN OF VOLTAGE CONTRAST PROCESS MONITOR (17958281)
- 1.51 SINGULATION OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES (17957355)
- 1.52 SINGULATION OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES (17957359)
- 1.53 MICROELECTRONICS PACKAGES WITH PHOTO-INTEGRATED GLASS INTERPOSER (17958002)
- 1.54 METHODS AND APPARATUSES FOR THROUGH-GLASS VIAS (17958053)
- 1.55 LAYERED GLASS ASSEMBLY WITH PRE-PATTERNED ELECTRICALLY CONDUCTIVE INTERCONNECTS (17955689)
- 1.56 DUAL SIDED EMBEDDED PASSIVES VIA PANEL LEVEL THERMAL COMPRESSION BONDING (17956421)
- 1.57 HYBRID BONDING TECHNOLOGIES WITH THERMAL EXPANSION COMPENSATION STRUCTURES (17957751)
- 1.58 PACKAGE ARCHITECTURE WITH DIE-TO-DIE COUPLING USING GLASS INTERPOSER (17937519)
- 1.59 AIR GAP ARCHITECTURE FOR HIGH SPEED I/O SUBSTRATE TRACES (17958012)
- 1.60 POROUS POLYMER DIELECTRIC LAYER ON CORE (17957637)
- 1.61 PLUG IN A METAL LAYER (17958288)
- 1.62 SPLIT VIA STRUCTURES COUPLED TO CONDUCTIVE LINES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION (17956775)
- 1.63 ULTRA-THIN SEMI-METALS FOR LOW TEMPERATURE CONDUCTION (17958283)
- 1.64 INCORPORATION OF SUPERLATTICE SEMI-METALS FOR SCALED INTERCONNECTS (17958284)
- 1.65 MULTICHIP IC DEVICES IN GLASS MEDIUM & INCLUDING AN INTERCONNECT BRIDGE DIE (17957783)
- 1.66 DYNAMIC RANDOM-ACCESS MEMORY IN A MOLDING BENEATH A DIE (17956753)
- 1.67 BACKSIDE WAFER TREATMENTS TO REDUCE DISTORTIONS AND OVERLAY ERRORS DURING WAFER CHUCKING (17957552)
- 1.68 EMBEDDED THIN FILM VARISTOR IN THROUGH GLASS VIAS (17957257)
- 1.69 INTEGRATED POWER DELIVERY REGULATION CIRCUITS IN GLASS CORE USING EMBEDDED ACTIVE AND PASSIVE COMPONENTS (17957225)
- 1.70 INTEGRATED HORIZONTAL VARISTOR ON GLASS CORE FOR VOLTAGE REGULATION (17957590)
- 1.71 PACKAGE SUBSTRATE WITH OPEN AIR GAP STRUCTURES (17937474)
- 1.72 SEMICONDUCTOR PACKAGES WITH ANTENNAS (18541878)
- 1.73 SINGULATION OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES (17957349)
- 1.74 SIDE OF A DIE THAT IS COPLANAR WITH A SIDE OF A MOLDING (17956760)
- 1.75 MULTICHIP IC DEVICES WITH DIE EMBEDDED IN GLASS SUBSTRATE & A REDISTRIBUTION LAYER INTERCONNECT BRIDGE (17956363)
- 1.76 HIGH PERFORMANCE PERMANENT GLASS ARCHITECTURES FOR STACKED INTEGRATED CIRCUIT DEVICES (17957403)
- 1.77 INTEGRATED CIRCUIT PACKAGES WITH HYBRID BONDED DIES AND METHODS OF MANUFACTURING THE SAME (17957926)
- 1.78 CAPACITOR STRUCTURE EMBEDDED WITHIN SOURCE OR DRAIN REGION (17936990)
- 1.79 FORKSHEET TRANSISTOR STRUCTURES WITH GATE CUT SPINE (17936952)
- 1.80 FORMING METAL GATE CUTS USING MULTIPLE PASSES FOR DEPTH CONTROL (17937212)
- 1.81 ETCH STOP LAYER FOR METAL GATE CUT (17957106)
- 1.82 GATE CUT, WITH ASYMMETRICAL CHANNEL TO GATE CUT SPACING (17957821)
- 1.83 WALL THAT INCLUDES A GAS BETWEEN METAL GATES OF A SEMICONDUCTOR DEVICE (17958285)
- 1.84 PLUG BETWEEN TWO GATES OF A SEMICONDUCTOR DEVICE (17958291)
- 1.85 INTEGRATED CIRCUIT STRUCTURES HAVING FIN ISOLATION REGIONS RECESSED FOR GATE CONTACT (17956779)
- 1.86 EPITAXIAL STRUCTURE AND GATE METAL STRUCTURES WITH A PLANAR TOP SURFACE (17958293)
- 1.87 ULTRA-LOW VOLTAGE TRANSISTOR CELL DESIGN USING GATE CUT LAYOUT (17956188)
- 1.88 FABRICATION OF RECONFIGURABLE ARCHITECTURES USING FERROELECTRICS (17957836)
- 1.89 HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS (18538795)
- 1.90 HIGH SURFACE AREA CAPACITOR IN AN ELECTRONIC SUBSTRATE PACKAGE (17957003)
- 1.91 TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN (18540544)
- 1.92 STACKED SOURCE OR DRAIN CONTACT FLYOVER (17957887)
- 1.93 SQUARE ETCH PROFILES IN HETEROGENOUS MATERIALS OF INTEGRATED CIRCUIT DEVICES (17957580)
- 1.94 TECHNOLOGIES FOR PEROVSKITE TRANSISTORS (17956296)
- 1.95 TECHNOLOGIES FOR TRANSISTORS WITH A THIN-FILM FERROELECTRIC (17958094)
- 1.96 WALL COUPLED WITH TWO STACKS OF NANORIBBONS TO ELECTRICAL ISOLATE GATE METALS (17958290)
- 1.97 PACKAGE INTEGRATED MULTIBAND AND POLARIZATION DIVERSIFIED MODE RECONFIGURABLE ANTENNA SYSTEM FOR ROBUST WIRELESS CHIP TO CHIP COMMUNICATION (17955551)
- 1.98 SOCKET INTERCONNECT STRUCTURES AND RELATED METHODS (17957761)
- 1.99 APPARATUS, SYSTEM, AND METHOD OF A MULTI-MODE POWER AMPLIFIER (17957011)
- 1.100 APPARATUS, SYSTEM AND METHOD OF PHASE SHIFTING (17958340)
- 1.101 IN-MEMORY ANALOG CHANNEL EQUALIZATION (17956844)
- 1.102 Flexible Circuit for Real and Complex Filter Operations (17957339)
- 1.103 TECHNIQUES FOR DUTY CYCLE CORRECTION (18534430)
- 1.104 EMBEDDED SAR-ADC WITH LEAST SIGNIFICANT BIT SKIPPING BASED RELU ACTIVATION FUNCTION (18539957)
- 1.105 ACTIVE ELECTRONIC SIGNAL CROSSTALK CANCELLATION (17957053)
- 1.106 ENHANCED LOW COMPLEXITY LOW-DENSITY PARITY-CHECK ENCODING PROCESS FOR ULTRA HIGH RELIABILITY (18522065)
- 1.107 WIRELESS DEVICE AND METHODS FOR DYNAMIC CHANNEL CODING (18448183)
- 1.108 ENCRYPTED PROCESSING UNIT EMULATED WITH HOMOMORPHIC ENCRYPTION CIRCUITS (17937258)
- 1.109 EFFICIENT IMPLEMENTATION OF ZUC AUTHENTICATION (18129814)
- 1.110 POST-QUANTUM LATTICE-BASED SIGNATURE LATENCY REDUCTION (17936049)
- 1.111 TECHNOLOGIES FOR DYNAMICALLY MANAGING RESOURCES IN DISAGGREGATED ACCELERATORS (18388461)
- 1.112 METHODS AND APPARATUS FOR IDENTITY AND ACCESS MANAGEMENT ON NETWORKED MACHINES (18538973)
- 1.113 Apparatus for providing a connection to a wide area network for voice calls, a power management circuit, and a method for providing a connection to a wide area network for voice calls (18473321)
- 1.114 MULTI-LINK OPERATION TRANSMIT ARCHITECTURE FOR DYNAMIC MAPPING OF TRANSMIT QUEUES TO LINKS (17956950)
- 1.115 MULTI-TTI SCHEDULING OF PDSCH AND PUSCH BY DCI (18280808)
- 1.116 BEAM MANAGEMENT WITH FLEXIBLE BEAM-FORMING ASSIGNMENT (18530754)
- 1.117 EMBEDDED PASSIVES WITH CAVITY SIDEWALL INTERCONNECT IN GLASS CORE ARCHITECTURE (17956338)
- 1.118 HYBRID BONDED PASSIVE INTEGRATED DEVICES ON GLASS CORE (17956384)
- 1.119 ENHANCED SUBTRACTIVE ETCH ANISOTROPY USING ETCH RATE GRADIENT (17937894)
- 1.120 INVERTED FERROELECTRIC AND ANTIFERROLECETRIC CAPACITORS (17958395)
- 1.121 SELF-ALIGNED PATTERNING OF PLATE LINES IN THREE-DIMENSIONAL FERROELECTRIC CAPACITORS (17958202)
- 1.122 FERROELECTRIC CAPACITOR WITHIN BACKSIDE INTERCONNECT (17937043)
- 1.123 HIGH ENDURANCE SUPER-LATTICE ANTI-FERROELECTRIC CAPACITORS (17957560)
- 1.124 IMPROVED REPLACEMENT ELECTRODE PROCESS FOR 3D FERROELECTRIC MEMORY (17957603)
- 1.125 GAIN CELL USING PLANAR AND TRENCH FERROELECTRIC AND ANTI-FERROELECTRIC CAPACITORS FOR EDRAM (17958279)
Patent applications for Intel Corporation on April 4th, 2024
REAL-TIME AUTONOMOUS SEAT ADAPTATION AND IMMERSIVE CONTENT DELIVERY FOR VEHICLES (17956485)
Main Inventor
Rajesh Poornachandran
Secure Remote Debugging (17958071)
Main Inventor
Tsvika Kurts
NANOROD COATING BETWEEN TWO OPTICAL MEDIUMS (17956750)
Main Inventor
Yi YANG
DIRECTLY COUPLED OPTICAL INTERPOSER (17957341)
Main Inventor
Robert A. May
PILLAR STRUCTURES ON AN OPTICAL WAVEGUIDE (17956757)
Main Inventor
Brandon C. MARIN
GLASS RECIRCULATOR FOR OPTICAL SIGNAL REROUTING ACROSS PHOTONIC INTEGRATED CIRCUITS (17957094)
Main Inventor
Benjamin Duong
HYBRID PLASMONIC WAVEGUIDE AND METHOD FOR HIGH DENSITY PACKAGING INTEGRATED WITH A GLASS INTERPOSER (17957600)
Main Inventor
Hiroki Tanaka
METHOD AND DEVICE FOR FAST, PASSIVE ALIGNMENT IN PHOTONICS ASSEMBLY (18488074)
Main Inventor
Vineeth ABRAHAM
INTELLIGENT AND ADAPTIVE MULTI-MODAL REAL-TIME SIMULTANEOUS LOCALIZATION AND MAPPING BASED ON LIGHT DETECTION AND RANGING AND CAMERA OR IMAGE SENSORS (17954372)
Main Inventor
Mohammad HAGHIGHIPANAH
METHODS AND APPARATUS TO OPERATE CLOSED-LID PORTABLE COMPUTERS (18525248)
Main Inventor
Barnes Cooper
CHIP AND PLATFORM LEVEL POWER MONITORING AND SEQUENCING FOR ROBUST STARTUP AND MODE SWITCHING (17957052)
Main Inventor
Deepak Dasalukunte
DATA CENTER POWER CONSUMPTION THROUGH MODULATION OF POWER SUPPLY UNIT CONVERSION FREQUENCY (18537740)
Main Inventor
Sakthi Priyan B S
CONSTRUCTING HIERARCHICAL CLOCK GATING ARCHITECTURES VIA REWRITING (18538116)
Main Inventor
Samuel Coward
TECHNIQUES TO REDUCE POWER CONSUMPTION FOR A DISTRIBUTED COMPUTATIONAL MODEL MAPPED ONTO A MULTI-PROCESSING NODE SYSTEM (17958108)
Main Inventor
Javier MARTIN LANGERWERF
STORAGE COMMAND COMPRISING TIME PARAMETER (18532491)
Main Inventor
Daniel Christian Biederman
Apparatus, Device, Method and Computer Program for Generating Code using an LLM (18536299)
Main Inventor
Robert VAUGHN
FREQUENCY SCALING FOR PER-CORE ACCELERATOR ASSIGNMENTS (18369082)
Main Inventor
Stephen T. PALERMO
SYSTEMS, METHODS, AND APPARATUS FOR TILE CONFIGURATION (18534012)
Main Inventor
Menachem ADELMAN
DETERMINISTIC BROADCASTING FROM SHARED MEMORY (17957486)
Main Inventor
Fangwen Fu
DEVICE, METHOD AND SYSTEM TO DETERMINE A MODE OF PROCESSOR OPERATION BASED ON PAGE TABLE METADATA (17957969)
Main Inventor
Jason Agron
CIRCUITRY TO PERFORM PARTIAL DECOMPRESSION OPERATIONS (18526910)
Main Inventor
Marian HORGAN
ORDERED THREAD DISPATCH FOR THREAD TEAMS (17937270)
Main Inventor
Biju George
SEQUENCING CIRCUIT FOR A PROCESSOR (17957919)
Main Inventor
Shidlingeshwar Khatakalle
SYNCHRONIZATION UTILIZING LOCAL TEAM BARRIERS FOR THREAD TEAM PROCESSING (17958213)
Main Inventor
Biju George
DYNAMIC APPLICATION PROGRAMMING INTERFACE (API) CONTRACT GENERATION AND CONVERSION THROUGH MICROSERVICE SIDECARS (18541245)
Main Inventor
Marcos Carranza
HYBRID PERFORMANCE MONITORING UNIT (PMU) ENUMERATION (18374296)
Main Inventor
Raoul Rivas Toledano
DEVICE, METHOD, AND SYSTEM TO DETERMINE A COUNT OF RETIRED PREFETCH INSTRUCTIONS (17957978)
Main Inventor
Ahmad Yasin
HARDWARE PROCESSOR HAVING MULTIPLE MEMORY PREFETCHERS AND MULTIPLE PREFETCH FILTERS (17958334)
Main Inventor
Seth Pugsley
TIME-AWARE NETWORK DATA TRANSFER (18532079)
Main Inventor
Daniel Christian Biederman
DYNAMIC SWITCHING OF DATA TRANSFERS BETWEEN SIDEBAND AND MAINBAND (18539063)
Main Inventor
Aruni P. Nelson
SINGLE PRECISION SUPPORT FOR SYSTOLIC PIPELINE IN A GRAPHICS ENVIRONMENT (17937229)
Main Inventor
Jiasheng Chen
HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT (17937252)
Main Inventor
Jiasheng Chen
ACCURACY-BASED APPROXIMATION OF ACTIVATION FUNCTIONS WITH PROGRAMMABLE LOOK-UP TABLE HAVING AREA BUDGET (18534035)
Main Inventor
Umer Iftikhar Cheema
PROTECTED DATA ACCESSES USING REMOTE COPY OPERATIONS (18370137)
Main Inventor
Ned SMITH
HARDWARE POWER OPTIMIZATION VIA E-GRAPH BASED AUTOMATIC RTL EXPLORATION (18538104)
Main Inventor
Samuel Coward
DEEP LEARNING HARDWARE (18534566)
Main Inventor
Horace H. Lau
HARDWARE IP OPTIMIZED CONVOLUTIONAL NEURAL NETWORK (18514069)
Main Inventor
Amit Bleiweiss
3D OBJECT RECOGNITION USING 3D CONVOLUTIONAL NEURAL NETWORK WITH DEPTH BASED MULTI-SCALE FILTERS (18527490)
Main Inventor
Ganmei YOU
REAL-TIME SITUATIONAL PLANNING FOR PASSENGER TRANSPORT (17955549)
Main Inventor
Fabian OBORIL
SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING (17958216)
Main Inventor
Biju George
HUMAN-ROBOT INTERACTIVE WORKSPACE (17957529)
Main Inventor
David Gonzalez Aguirre
APPARATUS, METHOD, AND COMPUTER-READABLE MEDIUM FOR ROBUST RESPONSE TO ADVERSARIAL PERTURBATIONS USING HYPERDIMENSIONAL VECTORS (18478335)
Main Inventor
Narayan Srinivasa
Scalable Digital Twin Services for intelligent transport systems (ITS) with Optimized Communication and Dynamic Resource Adaptation (17936438)
Main Inventor
Ned M. Smith
SELECTIVE FERROELECTRIC DEPLOYMENT FOR SINGLE-TRANSISTOR, MULTIPLE-CAPACITOR DEVICES (17957591)
Main Inventor
Nazila Haratipour
DEVICE, METHOD AND SYSTEM TO PROVIDE A RANDOM ACCESS MEMORY WITH A FERROELECTRIC RESISTIVE JUNCTION (17957945)
Main Inventor
Sou-Chi Chang
MEMORY ARRAY COMPRISING A FERROELECTRIC DATA STORAGE ELEMENT (17957957)
Main Inventor
Sou-Chi Chang
METAL GATE CUT FORMED AFTER SOURCE AND DRAIN CONTACTS (17936934)
Main Inventor
Swapnadip Ghosh
INTEGRATED CIRCUIT INTERCONNECT STRUCTURES WITH NIOBIUM BARRIER MATERIALS (17957721)
Main Inventor
Philip Yashar
INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORES (18535623)
Main Inventor
Hui Jae YOO
DESIGN OF VOLTAGE CONTRAST PROCESS MONITOR (17958281)
Main Inventor
Xiao WEN
SINGULATION OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES (17957355)
Main Inventor
Hanyu Song
SINGULATION OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES (17957359)
Main Inventor
Yiqun Bai
MICROELECTRONICS PACKAGES WITH PHOTO-INTEGRATED GLASS INTERPOSER (17958002)
Main Inventor
Hiroki Tanaka
METHODS AND APPARATUSES FOR THROUGH-GLASS VIAS (17958053)
Main Inventor
Jeremy D. Ecton
LAYERED GLASS ASSEMBLY WITH PRE-PATTERNED ELECTRICALLY CONDUCTIVE INTERCONNECTS (17955689)
Main Inventor
Jieying Kong
DUAL SIDED EMBEDDED PASSIVES VIA PANEL LEVEL THERMAL COMPRESSION BONDING (17956421)
Main Inventor
Kristof Darmawikarta
HYBRID BONDING TECHNOLOGIES WITH THERMAL EXPANSION COMPENSATION STRUCTURES (17957751)
Main Inventor
Jeremy Ecton
PACKAGE ARCHITECTURE WITH DIE-TO-DIE COUPLING USING GLASS INTERPOSER (17937519)
Main Inventor
Brandon C. Marin
AIR GAP ARCHITECTURE FOR HIGH SPEED I/O SUBSTRATE TRACES (17958012)
Main Inventor
Benjamin Duong
POROUS POLYMER DIELECTRIC LAYER ON CORE (17957637)
Main Inventor
Whitney Bryks
PLUG IN A METAL LAYER (17958288)
Main Inventor
Leonard P. GULER
SPLIT VIA STRUCTURES COUPLED TO CONDUCTIVE LINES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION (17956775)
Main Inventor
Leonard P. GULER
ULTRA-THIN SEMI-METALS FOR LOW TEMPERATURE CONDUCTION (17958283)
Main Inventor
Abhishek Anil SHARMA
INCORPORATION OF SUPERLATTICE SEMI-METALS FOR SCALED INTERCONNECTS (17958284)
Main Inventor
Abhishek Anil SHARMA
MULTICHIP IC DEVICES IN GLASS MEDIUM & INCLUDING AN INTERCONNECT BRIDGE DIE (17957783)
Main Inventor
Jeremy Ecton
DYNAMIC RANDOM-ACCESS MEMORY IN A MOLDING BENEATH A DIE (17956753)
Main Inventor
Eng Huat GOH
BACKSIDE WAFER TREATMENTS TO REDUCE DISTORTIONS AND OVERLAY ERRORS DURING WAFER CHUCKING (17957552)
Main Inventor
Tayseer Mahdi
EMBEDDED THIN FILM VARISTOR IN THROUGH GLASS VIAS (17957257)
Main Inventor
Jason Scott Steill
INTEGRATED POWER DELIVERY REGULATION CIRCUITS IN GLASS CORE USING EMBEDDED ACTIVE AND PASSIVE COMPONENTS (17957225)
Main Inventor
Srinivasan Raman
INTEGRATED HORIZONTAL VARISTOR ON GLASS CORE FOR VOLTAGE REGULATION (17957590)
Main Inventor
Srinivasan Raman
PACKAGE SUBSTRATE WITH OPEN AIR GAP STRUCTURES (17937474)
Main Inventor
Kristof Kuwawi Darmawikarta
SEMICONDUCTOR PACKAGES WITH ANTENNAS (18541878)
Main Inventor
Telesphor Kamgaing
SINGULATION OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES (17957349)
Main Inventor
Whitney Bryks
SIDE OF A DIE THAT IS COPLANAR WITH A SIDE OF A MOLDING (17956760)
Main Inventor
Xavier F. BRUN
MULTICHIP IC DEVICES WITH DIE EMBEDDED IN GLASS SUBSTRATE & A REDISTRIBUTION LAYER INTERCONNECT BRIDGE (17956363)
Main Inventor
Jeremy Ecton
HIGH PERFORMANCE PERMANENT GLASS ARCHITECTURES FOR STACKED INTEGRATED CIRCUIT DEVICES (17957403)
Main Inventor
Brandon Marin
INTEGRATED CIRCUIT PACKAGES WITH HYBRID BONDED DIES AND METHODS OF MANUFACTURING THE SAME (17957926)
Main Inventor
Omkar Karhade
CAPACITOR STRUCTURE EMBEDDED WITHIN SOURCE OR DRAIN REGION (17936990)
Main Inventor
Sourav Dutta
FORKSHEET TRANSISTOR STRUCTURES WITH GATE CUT SPINE (17936952)
Main Inventor
Sukru Yemenicioglu
FORMING METAL GATE CUTS USING MULTIPLE PASSES FOR DEPTH CONTROL (17937212)
Main Inventor
Alison V. Davis
ETCH STOP LAYER FOR METAL GATE CUT (17957106)
Main Inventor
Sukru Yemenicioglu
GATE CUT, WITH ASYMMETRICAL CHANNEL TO GATE CUT SPACING (17957821)
Main Inventor
Sukru Yemenicioglu
WALL THAT INCLUDES A GAS BETWEEN METAL GATES OF A SEMICONDUCTOR DEVICE (17958285)
Main Inventor
Sukru YEMENICIOGLU
PLUG BETWEEN TWO GATES OF A SEMICONDUCTOR DEVICE (17958291)
Main Inventor
Leonard P. GULER
INTEGRATED CIRCUIT STRUCTURES HAVING FIN ISOLATION REGIONS RECESSED FOR GATE CONTACT (17956779)
Main Inventor
Leonard P. GULER
EPITAXIAL STRUCTURE AND GATE METAL STRUCTURES WITH A PLANAR TOP SURFACE (17958293)
Main Inventor
Dan S. LAVRIC
ULTRA-LOW VOLTAGE TRANSISTOR CELL DESIGN USING GATE CUT LAYOUT (17956188)
Main Inventor
Tao Chu
FABRICATION OF RECONFIGURABLE ARCHITECTURES USING FERROELECTRICS (17957836)
Main Inventor
Elijah V. Karpov
HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS (18538795)
Main Inventor
Walid M. HAFEZ
HIGH SURFACE AREA CAPACITOR IN AN ELECTRONIC SUBSTRATE PACKAGE (17957003)
Main Inventor
Jeremy D. Ecton
TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN (18540544)
Main Inventor
Willy RACHMADY
STACKED SOURCE OR DRAIN CONTACT FLYOVER (17957887)
Main Inventor
Sukru Yemenicioglu
SQUARE ETCH PROFILES IN HETEROGENOUS MATERIALS OF INTEGRATED CIRCUIT DEVICES (17957580)
Main Inventor
Mekha George
TECHNOLOGIES FOR PEROVSKITE TRANSISTORS (17956296)
Main Inventor
Ian Alexander Young
TECHNOLOGIES FOR TRANSISTORS WITH A THIN-FILM FERROELECTRIC (17958094)
Main Inventor
Arnab Sen Gupta
WALL COUPLED WITH TWO STACKS OF NANORIBBONS TO ELECTRICAL ISOLATE GATE METALS (17958290)
Main Inventor
Leonard P. GULER
PACKAGE INTEGRATED MULTIBAND AND POLARIZATION DIVERSIFIED MODE RECONFIGURABLE ANTENNA SYSTEM FOR ROBUST WIRELESS CHIP TO CHIP COMMUNICATION (17955551)
Main Inventor
Zhen ZHOU
SOCKET INTERCONNECT STRUCTURES AND RELATED METHODS (17957761)
Main Inventor
Kai Xiao
APPARATUS, SYSTEM, AND METHOD OF A MULTI-MODE POWER AMPLIFIER (17957011)
Main Inventor
Ofir Degani
APPARATUS, SYSTEM AND METHOD OF PHASE SHIFTING (17958340)
Main Inventor
Elan Banin
IN-MEMORY ANALOG CHANNEL EQUALIZATION (17956844)
Main Inventor
Richard DORRANCE
Flexible Circuit for Real and Complex Filter Operations (17957339)
Main Inventor
Martin Langhammer
TECHNIQUES FOR DUTY CYCLE CORRECTION (18534430)
Main Inventor
Christopher P. MOZAK
EMBEDDED SAR-ADC WITH LEAST SIGNIFICANT BIT SKIPPING BASED RELU ACTIVATION FUNCTION (18539957)
Main Inventor
Hechen Wang
ACTIVE ELECTRONIC SIGNAL CROSSTALK CANCELLATION (17957053)
Main Inventor
Harry Muljono
ENHANCED LOW COMPLEXITY LOW-DENSITY PARITY-CHECK ENCODING PROCESS FOR ULTRA HIGH RELIABILITY (18522065)
Main Inventor
Juan FANG
WIRELESS DEVICE AND METHODS FOR DYNAMIC CHANNEL CODING (18448183)
Main Inventor
Richard DORRANCE
ENCRYPTED PROCESSING UNIT EMULATED WITH HOMOMORPHIC ENCRYPTION CIRCUITS (17937258)
Main Inventor
Bradley Smith
EFFICIENT IMPLEMENTATION OF ZUC AUTHENTICATION (18129814)
Main Inventor
Pablo De Lara Guarch
POST-QUANTUM LATTICE-BASED SIGNATURE LATENCY REDUCTION (17936049)
Main Inventor
ZACHARY PEPIN
TECHNOLOGIES FOR DYNAMICALLY MANAGING RESOURCES IN DISAGGREGATED ACCELERATORS (18388461)
Main Inventor
Francesc GUIM BERNAT
METHODS AND APPARATUS FOR IDENTITY AND ACCESS MANAGEMENT ON NETWORKED MACHINES (18538973)
Main Inventor
Christopher Son Thach
Apparatus for providing a connection to a wide area network for voice calls, a power management circuit, and a method for providing a connection to a wide area network for voice calls (18473321)
Main Inventor
Dieter Foedlmeier
MULTI-LINK OPERATION TRANSMIT ARCHITECTURE FOR DYNAMIC MAPPING OF TRANSMIT QUEUES TO LINKS (17956950)
Main Inventor
Danny Alexander
MULTI-TTI SCHEDULING OF PDSCH AND PUSCH BY DCI (18280808)
Main Inventor
Yingyang Li
BEAM MANAGEMENT WITH FLEXIBLE BEAM-FORMING ASSIGNMENT (18530754)
Main Inventor
Alexei Davydov
EMBEDDED PASSIVES WITH CAVITY SIDEWALL INTERCONNECT IN GLASS CORE ARCHITECTURE (17956338)
Main Inventor
Kristof Darmawikarta
HYBRID BONDED PASSIVE INTEGRATED DEVICES ON GLASS CORE (17956384)
Main Inventor
Kristof Darmawikarta
ENHANCED SUBTRACTIVE ETCH ANISOTROPY USING ETCH RATE GRADIENT (17937894)
Main Inventor
Jeremy Ecton
INVERTED FERROELECTRIC AND ANTIFERROLECETRIC CAPACITORS (17958395)
Main Inventor
Nazila Haratipour
SELF-ALIGNED PATTERNING OF PLATE LINES IN THREE-DIMENSIONAL FERROELECTRIC CAPACITORS (17958202)
Main Inventor
Christopher M. Neumann
FERROELECTRIC CAPACITOR WITHIN BACKSIDE INTERCONNECT (17937043)
Main Inventor
Sourav Dutta
HIGH ENDURANCE SUPER-LATTICE ANTI-FERROELECTRIC CAPACITORS (17957560)
Main Inventor
Sou-Chi Chang
IMPROVED REPLACEMENT ELECTRODE PROCESS FOR 3D FERROELECTRIC MEMORY (17957603)
Main Inventor
Christopher Neumann
GAIN CELL USING PLANAR AND TRENCH FERROELECTRIC AND ANTI-FERROELECTRIC CAPACITORS FOR EDRAM (17958279)
Main Inventor
Shriram SHIVARAMAN