Intel Corporation patent applications on April 11th, 2024
Patent Applications by Intel Corporation on April 11th, 2024
Intel Corporation: 37 patent applications
Intel Corporation has applied for patents in the areas of G06N3/04 (8), G06N3/063 (6), G06N3/08 (4), G06F1/3296 (4), G06F1/329 (4)
With keywords such as: data, device, memory, circuitry, network, based, signal, apparatus, layer, and input in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Abhinandan GUJJAR of Bangalore (IN) for intel corporation, Ashok Kumar KALADI of Bangalore (IN) for intel corporation
IPC Code(s): G06F1/329, G06F1/3296, G06F11/34
Abstract: methods, apparatus, and computer programs are disclosed for managing processor power consumption based on message queue utilization. in one embodiment, a method comprising: distributing messages to a set of processor cores of a processor, wherein one message is distributed per distribution round to one queue within a set of queues, each queue corresponding to one processor core within the set of processor cores and including one or more queue entries to be processed by the one processor core, and where the distribution is based on utilization of the set of queues; based on utilization of a corresponding queue for a processor core of the set of processor cores, determining a power state for the processor core to be changed to; and distributing a message to the corresponding queue, the message to cause the processor core to be set to the power state.
Inventor(s): Amlan Ghosh of Mebane NC (US) for intel corporation, Feroze Merchant of Austin TX (US) for intel corporation, Jaydeep Kulkarni of Austin TX (US) for intel corporation, John R. Riley of Sebastian FL (US) for intel corporation
IPC Code(s): G06F3/06
Abstract: a memory device includes at least one bitcell coupled to a local bitline. the at least one bitcell includes multiple sets of a plurality of transistor devices. the first set of the plurality of transistor devices is configured to form a single write (1w) port for receiving digital data. the second set of the plurality of transistor devices is configured as an inverter pair. the inverter pair stores the digital data. the third set of the plurality of transistor devices is configured to form a single read (1r) port. the 1r port can be used to access the digital data stored at the inverter pair and output the digital data on the local bitline. the plurality of transistor devices includes an equal number of p-channel transistor devices and n-channel transistor devices.
Inventor(s): Martin Langhammer of Alderbury (GB) for intel corporation
IPC Code(s): G06F7/544, G06F30/34
Abstract: integrated circuit devices, methods, and circuitry for a digital signal processing (dsp) block that can selectively perform higher-precision dsp multiplication operations or lower-precision ai tensor multiplication operations. flexible digital signal processing circuitry may include hardened multipliers, hardened summation circuitry, and an intermediate multiplexer network. the intermediate multiplexer network may be configurable to, in a first configuration, route data between the plurality of hardened multipliers and the hardened summation circuitry to perform a plurality of lower-precision multiplication operations. in a second configuration, the intermediate multiplexer network may route the data between the plurality of hardened multipliers and the hardened summation circuitry to perform at least one higher-precision multiplication operation.
Inventor(s): Swagath VENKATARAMANI of Tirupur (IN) for intel corporation, Dipankar DAS of Pune (IN) for intel corporation, Ashish RANJAN of West Lafayette IN (US) for intel corporation, Subarno BANERJEE of Kolkata (IN) for intel corporation, Sasikanth AVANCHA of Malur Taluk (IN) for intel corporation, Ashok JAGANNATHAN of Bangalore (IN) for intel corporation, Ajaya V. DURG of Austin TX (US) for intel corporation, Dheemanth NAGARAJ of Bangalore (IN) for intel corporation, Bharat KAUL of Bengaluru (IN) for intel corporation, Anand RAGHUNATHAN of West Lafayette IN (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/38, G06F9/52, G06N3/04, G06N3/063, G06N3/084
Abstract: methods and apparatuses relating to processing neural networks are described. in one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.
20240118898.SELECTIVE USE OF BRANCH PREDICTION HINTS_simplified_abstract_(intel corporation)
Inventor(s): Jared W. Stark of Portland OR (US) for intel corporation, Ahmad Yasin of Kafr Manda (IL) for intel corporation, Ajay Amarsingh Singh of Rancho Cordova CA (US) for intel corporation
IPC Code(s): G06F9/38, G06F9/30, G06F12/0804
Abstract: embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. in an embodiment, an apparatus includes an instruction decoder and a branch predictor. the instruction decoder is to decode a branch instruction having a hint. the branch predictor is to provide a prediction and a hint-override indicator. the hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. the prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.
Inventor(s): Kishore Kasichainula of Phoenix AZ (US) for intel corporation, Kar Leong Wong of Folsom CA (US) for intel corporation, Nagaramya Jayagopal of Karlsruhe (DE) for intel corporation, Shravan Suryanarayana of Karlsruhe (DE) for intel corporation
IPC Code(s): G06F9/4401, G06F3/16
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to accelerate service execution. an example apparatus includes a system including first circuitry to initialize during a boot time period, and at least one of audio circuitry and networking circuitry to complete initialization and perform a service before expiration of the boot time period.
Inventor(s): Kaijie GUO of Shanghai (CN) for intel corporation, Junyuan WANG of Shanghai (CN) for intel corporation, Maksim LUKOSHKOV of Clarecastle, Clare (IE) for intel corporation, Weigang LI of Shanghai (CN) for intel corporation, Xin ZENG of Shanghai (CN) for intel corporation
IPC Code(s): G06F9/455
Abstract: an apparatus and method to implement shared virtual memory in a trust zone. for example, one embodiment of a processor comprises: a plurality of cores; a memory controller coupled to the plurality of cores to establish a first private memory region in a system memory using a first key associated with a first trust domain of a first guest; an input/output memory management unit (iommu) coupled to the memory controller, the iommu to receive a memory access request by an input/output (io) device, the memory access request comprising a first address space identifier and a guest virtual address (gva), the iommu to access an entry in a first translation table using at least the first address space identifier to determine that the memory access request is directed to the first private memory region which is not directly accessible to the iommu, the iommu to generate an address translation request associated with the memory access request, wherein based on the address translation request, a virtual machine monitor (vmm) running on one or more of the plurality of cores is to initiate a secure transaction sequence with trust domain manager to cause a secure entry into the first trust domain to translate the gva to a physical address based on the address space identifier, the iommu to receive the physical address from the vmm and to use the physical address to perform the requested memory access on behalf of the io device.
Inventor(s): Yi Wang of Shanghai (CN) for intel corporation, Yih Leong Sun of Beaverton OR (US) for intel corporation, Patrick L. Connor of Beaverton OR (US) for intel corporation
IPC Code(s): G06F9/455, H04L9/08
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed for deployment of a container in a network-constrained environment. an example apparatus includes interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to access a first unencrypted shared file, access a second encrypted file, create a third file by integrating contents of the first file and the second file, the third file being a virtual execution environment (vee) image, store the third file, and deploy the third file to a container runtime environment for execution.
Inventor(s): Guy M. Therien of Sherwood OR (US) for intel corporation, Michael D. Powell of Northborough MA (US) for intel corporation, Venkatesh Ramani of Milpitas CA (US) for intel corporation, Arijit Biswas of Northborough MA (US) for intel corporation, Guy G. Sotomayor of San Jose CA (US) for intel corporation
IPC Code(s): G06F9/50, G06F1/324, G06F1/329, G06F1/3296, G06F9/30
Abstract: apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. in embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. the one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. in some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.
Inventor(s): Ricardo SANDOVAL TORRES of Zapopan (MX) for intel corporation, Jose De Jesus PEREZ SEVILLA of Guadalajara (MX) for intel corporation, Jorge HERRERA FIGUEROA of Zapopan (MX) for intel corporation
IPC Code(s): G06F11/10, G06F11/16
Abstract: examples include techniques for memory scrubbing associated with reliability, availability and serviceability (ras) features. examples include obtaining error correction code (ecc) encoded data stored in a physical memory unit maintained in a physical memory device in associated with a memory scrubbing operation. examples include correcting detected errors in ecc encoded data and cause the corrected or scrubbed ecc encoded data to be stored in the physical memory unit. examples include obtaining the scrubbed ecc encoded data from the physical memory unit and responsive to at least one detected error in the scrubbed ecc encoded data, trigger one or more ras features.
Inventor(s): Martin-Thomas Grymel of Leixlip (IE) for intel corporation, David Bernard of Kilcullen (IE) for intel corporation, Martin Power of Dublin (IE) for intel corporation, Niall Hanrahan of Galway (IE) for intel corporation, Kevin Brady of Newry (GB) for intel corporation
IPC Code(s): G06F11/36, G06F11/277, G06F11/30, G06N3/04
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing artificial intelligence computational workloads. an example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. the debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. in response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.
Inventor(s): Shruti Sharma of Beaverton OR (US) for intel corporation, Robert Pawlowski of Beaverton OR (US) for intel corporation
IPC Code(s): G06F13/16, G06F9/52
Abstract: systems, apparatuses and methods may provide for technology that detects a condition in which a plurality of atomic instructions target a common address and different bit positions in a mask, generates a combined read-lock request for the plurality of atomic instructions in response to the condition, and sends the combined read-lock request to a lock buffer coupled to a memory device associated with the common address.
Inventor(s): Kevin C. SCOTT of Forest Grove OR (US) for intel corporation, Miles PENNER of Newberg OR (US) for intel corporation
IPC Code(s): G06F13/42
Abstract: examples described herein relate to utilizing a bus driver to present a peripheral device comprising a single physical function to a host operating system (os) as a plurality of peripheral devices, associating the plurality of presented peripheral devices with a corresponding plurality of physical ethernet ports; and enabling the host os to interact with the plurality of peripheral devices. in some examples, the number of the plurality of peripheral devices correlates to the number of physical ethernet ports associated with the peripheral device.
Inventor(s): Manish Dave of Folsom CA (US) for intel corporation, Vishwa Hassan of Chandler AZ (US) for intel corporation, Bhaskar D. Gowda of Hillsboro OR (US) for intel corporation, Mrigank Shekhar of Camas WA (US) for intel corporation
IPC Code(s): G06F21/60, H04L9/40, H04L67/10
Abstract: a device and method for provided access to distributed data sources includes a cloud security server configured to associate any number of data sources and client devices with a cloud security server account. the cloud security server assigns trust levels to the data sources and the client devices. a client device requests data from the cloud security server. the cloud security server authenticates the client device and verifies the trust levels of the client device and the requested data. if verified, the cloud security server brokers a connection between the client device and the data source, and the client device accesses the requested data. data sources may include cloud service providers and local storage devices. the cloud security server may assign a trust level to a client device for a limited time or revoke a trust level assigned to a client device. other embodiments are described and claimed.
Inventor(s): Yaniv Fais of Tel Aviv TA (IL) for intel corporation, Moshe Maor of Kiryat Mozking Z (IL) for intel corporation
IPC Code(s): G06N3/04, G06F8/41, G06F17/15, G06N3/063
Abstract: an example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.
Inventor(s): Estelle Aflalo of Haifa (IL) for intel corporation, Amit Bleiweiss of Yad Binyamin (IL) for intel corporation, Mattias Marder of Haifa (IL) for intel corporation, Eliran Zimmerman of Maalot (IL) for intel corporation
IPC Code(s): G06N3/063, G06F9/50, G06F18/21, G06N3/08
Abstract: methods, apparatus, systems and articles of manufacture are disclosed to map workloads. an example apparatus includes a constraint definer to define performance characteristic targets of the neural network, an action determiner to apply a first resource configuration to candidate resources corresponding to the neural network, a reward determiner to calculate a results metric based on (a) resource performance metrics and (b) the performance characteristic targets, and a layer map generator to generate a resource mapping file, the mapping file including respective resource assignments for respective corresponding layers of the neural network, the resource assignments selected based on the results metric.
Inventor(s): Ravi H. Motwani of Fremont CA (US) for intel corporation, Ke Ding of Saratoga CA (US) for intel corporation, Jian Zhang of Shanghai (CN) for intel corporation, Chendi Xue of Austin TX (US) for intel corporation, Poovaiah Manavattira Palangappa of San Jose CA (US) for intel corporation, Rita Brugarolas Brufau of Hillsboro OR (US) for intel corporation, Xinyao Wang of Shanghai (CN) for intel corporation, Yu Zhou of Shanghai (CN) for intel corporation, Aasavari Dhananjay Kakne of Santa Clara CA (US) for intel corporation
IPC Code(s): G06N3/08
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed that include interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to associate first datapoints of a first feature with a first node, associate second datapoints of a second feature with a second node, construct a graph from the first datapoints and the second datapoints, and perform a comparison of a graph accuracy with a baseline accuracy.
Inventor(s): Dmitry Kozlov of Nizhny Novgorod (RU) for intel corporation, Aleksei Chernigin of Nizhny Novgorod (RU) for intel corporation, Dmitry Tarakanov of Nizhny Novgorod (RU) for intel corporation
IPC Code(s): G06T3/4046, G06N3/04, G06N3/098, G06T1/20, G06T3/4053, G06T11/00, G06T11/20
Abstract: one embodiment provides a graphics processor comprising a set of processing resources configured to perform a supersampling anti-aliasing operation via a mixed precision convolutional neural network. the set of processing resources include circuitry configured to receive, at an input block of a neural network model, a set of data including previous frame data, current frame data, jitter offset data, and velocity data, pre-process the set of data to generate pre-processed data, provide pre-processed data to a feature extraction network of the neural network model and an output block of the neural network model, process the first pre-processed data at the feature extraction network via one or more encoder stages and one or more decoder stages, output tensor data from the feature extraction network to the output block, and generate an anti-aliased output frame via the output block based on the current frame data and the tensor data output from the feature extraction network.
Inventor(s): Ming Lu of Beijing (CN) for intel corporation, Liwei Liao of Beijing (CN) for intel corporation, Haihua Lin of Beijing (CN) for intel corporation, Xiaofeng Tong of Beijing (CN) for intel corporation, Wenlong Li of Beijing (CN) for intel corporation, Jiansheng Chen of Beijing (CN) for intel corporation, Yiwei He of Beijing (CN) for intel corporation
IPC Code(s): G06T7/73, G06V20/40
Abstract: a method and system of automatically estimating a ball carrier in team sports.
Inventor(s): Anmol Bhasin of SAS Nagar (IN) for intel corporation, Shekar Ramachandran of Bengaluru (IN) for intel corporation, Rudra Nath Palit of Kolkata (IN) for intel corporation, Rupali Agrahari of Sultanpur (IN) for intel corporation, Sai Pramod Gadam of Bengaluru (IN) for intel corporation
IPC Code(s): G06V10/774, G06V10/776, G06V10/82, G06V20/40, G06V40/16
Abstract: methods, systems, apparatus, and articles of manufacture to augment training data based on synthetic images are disclosed. an example apparatus disclosed herein includes programmable circuitry to generate, with one or more first layers of a generative adversarial network (gan), a latent representation corresponding to a first image representative of a first racial domain, generate, with one or more second layers of the gan, a second image based on the latent representation, the second image corresponding to a second racial domain different from the first racial domain, and augment a training dataset based on the second image.
Inventor(s): Muralidhar S. AMBATI of Hillsboro OR (US) for intel corporation, Ritesh JHAVERI of Hillsboro OR (US) for intel corporation, Moosung KIM of Portland OR (US) for intel corporation
IPC Code(s): H01L21/3065, H01L21/308, H01L21/311, H01L21/324, H01L29/06, H01L29/66
Abstract: embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. according to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. according to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. a first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. a second etching process is used to etch through the substrate to a second depth. according to embodiments of the invention, the first etching process utilizes an etching chemistry comprising hbr, oand cf, and the second etching process utilizes an etching chemistry comprising cl, ar, and ch.
Inventor(s): Krishna Bharath Kolluru of Portland OR (US) for intel corporation, Atul Maheshwari of Portland OR (US) for intel corporation, Mahesh Kumashikar of Bangalore (IN) for intel corporation, Md Altaf Hossain of Portland OR (US) for intel corporation, Ankireddy Nalamalpu of Portland OR (US) for intel corporation, Omkar Karhade of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L23/498
Abstract: an electronic device includes first and second external conductive pads coupled to route a first signal and third and fourth external conductive pads. the third and the fourth external conductive pads are between the first and the second external conductive pads on a surface of the electronic device.
Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Mohammad Mamunur Rahman of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L23/538
Abstract: embodiments of a microelectronic assembly includes: a package substrate and an integrated circuit (ic) die coupled to a surface of the package substrate by first interconnects and second interconnects, the first interconnects and the second interconnects comprising solder. the first interconnects are larger than the second interconnects, the first interconnects and the second interconnects further comprise bumps on the ic die and bond-pads on the surface of the package substrate, with the solder coupled to the bumps and the bond-pads, lateral sides of the bumps have a coating of a material that prevents solder wicking, and the surface of the package substrate includes insulative baffles between the bond-pads.
Inventor(s): Sudipto NASKAR of Portland OR (US) for intel corporation, Biswajeet GUHA of Hillsboro OR (US) for intel corporation, William HSU of Hillsboro OR (US) for intel corporation, Bruce BEATTIE of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/02, H01L21/8234, H01L29/06, H01L29/08, H01L29/66, H01L29/78
Abstract: gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. for example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. a gate stack is over the vertical arrangement of horizontal nanowires. a pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. a metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.
Inventor(s): Elliot TAN of Portland OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088, H01L29/40, H01L29/78
Abstract: contact over active gate (coag) structures with conductive gate taps are described. in an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. each of the plurality of gate structures includes a conductive tap structure protruding through the corresponding gate insulating layer. a plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. an interlayer dielectric material is above the trench insulating layers and the gate insulating layers. an opening is in the interlayer dielectric material and exposes the conductive tap structure of one of the plurality of gate structures. a conductive structure is in the opening and is in direct contact with the conductive tap structure of one of the plurality of gate structures.
Inventor(s): Scott B. Clendenning of Portland OR (US) for intel corporation, Sudarat Lee of Hillsboro OR (US) for intel corporation, Kevin P. O'Brien of Portland OR (US) for intel corporation, Rachel A. Steinhardt of Beaverton OR (US) for intel corporation, John J. Plombon of Portland OR (US) for intel corporation, Arnab Sen Gupta of Hillsboro OR (US) for intel corporation, Charles C. Mokhtarzadeh of Portland OR (US) for intel corporation, Gauri Auluck of Hillsboro OR (US) for intel corporation, Tristan A. Tronic of Aloha OR (US) for intel corporation, Brandon Holybee of Portland OR (US) for intel corporation, Matthew V. Metz of Portland OR (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation
IPC Code(s): H01L29/778, H01L21/02, H01L29/06, H01L29/66, H01L29/78
Abstract: technologies for a field effect transistor (fet) with a ferroelectric gate dielectric are disclosed. in an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. the perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. the lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon fet. a ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. a gate can then be grown on the ferroelectric layer.
20240120651.PHOTONICALLY STEERED IMPEDANCE SURFACE ANTENNAS_simplified_abstract_(intel corporation)
Inventor(s): Zhen Zhou of Chandler AZ (US) for intel corporation, Tae Young Yang of Portland OR (US) for intel corporation, Timo Huusari of Hillsboro OR (US) for intel corporation, Renzhi Liu of Portland OR (US) for intel corporation, Wei Qian of Walnut CA (US) for intel corporation, Mengyuan Huang of Cupertino CA (US) for intel corporation, Jason Mix of Portland OR (US) for intel corporation
IPC Code(s): H01Q3/26, H01L23/498, H01L23/66
Abstract: photonically steered impedance surface antennas are disclosed. a disclosed example apparatus includes a semiconductor substrate to be communicatively coupled to a radio frequency (rf) source, an at least partially transparent dielectric layer, the semiconductor substrate at a first side of the at least partially transparent dielectric layer, an at least partially transparent conductive film at a second side of the at least partially transparent dielectric layer that is opposite the first side of the at least partially transparent dielectric layer, and an illumination source to illuminate at least a portion of the semiconductor substrate to generate a photoinduced solid-state plasma pattern that beam steers an rf signal corresponding to the rf source.
Inventor(s): Ofir DEGANI of Haifa (IL) for intel corporation, Run LEVINGER of Portland OR (US) for intel corporation, Ashoke RAVI of Portland OR (US) for intel corporation
IPC Code(s): H03L7/099
Abstract: the present disclosure relates to a signal generator including: a plurality of interpolators, each interpolator being configured to: receive a first input signal having a first phase, and a second input signal having a second phase; generate a plurality of interpolated signals based on a plurality of interpolations of the input signals, each interpolated signal having a respective phase based on the respective interpolation, and combine the interpolated signals to provide an output signal; the plurality of interpolators including: a first plurality of interpolators, each interpolator being configured to receive as input signals a first reference signal and a second reference signal; and a second plurality of interpolators, each interpolator being configured to receive as first input signal an output signal from an interpolator of the first plurality of interpolators and as second input signal another output signal from another interpolator of the first plurality of interpolators.
Inventor(s): Assaf BEN-BASSAT of Haifa (IL) for intel corporation, Eli BOROKHOVICH of Modiin-Maccabim-Reu (IL) for intel corporation, Phillip SKLIAR of Holon (IL) for intel corporation
IPC Code(s): H04B17/10, G01R21/133, G01R25/00, H04B3/06, H04B17/14, H04L25/02
Abstract: an electronic circuitry is proposed. the electronic circuitry comprises a directional coupler comprising a first port configured to receive an input signal from a signal source, a second port configured to output the input signal for transmission to a load, a third port configured to output a forward signal based on the input signal, and a fourth port configured to output a reverse signal based on a reflection of the input signal received at the second port. the electronic circuitry further comprises a time-to-digital converter, tdc, coupled to the third port and the fourth port. the tdc is configured to determine a phase difference between the forward signal and the reverse signal.
20240121079.DATA CLEARING ATTESTATION_simplified_abstract_(intel corporation)
Inventor(s): Tat Kin Tan of Bayan Lepas (MY) for intel corporation, Chew Yee Kee of Bayan Lepas (MY) for intel corporation, Boon Khai Ng of Bayan Lepas (MY) for intel corporation
IPC Code(s): H04L9/06
Abstract: one or more non-transitory computer-readable media with instructions stored thereon, wherein the instructions are executable to cause one or more processor units to responsive to a data clear command issued by a tenant of a cloud service provider, issue a plurality of write commands to storage locations utilized by the tenant, the write commands to write a value based on an input provided by the tenant to the storage locations; and provide data read from at least a subset of the storage locations for attestation by the tenant of performance of the data clear command.
20240121097.INTEGRITY PROTECTED COMMAND BUFFER EXECUTION_simplified_abstract_(intel corporation)
Inventor(s): Pradeep M. Pappachan of Tualatin OR (US) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation
IPC Code(s): H04L9/32, G06F21/60, H04L9/08
Abstract: embodiments are directed to providing integrity-protected command buffer execution. an embodiment of an apparatus includes a computer-readable memory comprising one or more command buffers and a processing device communicatively coupled to the computer-readable memory to read, from a command buffer of the computer-readable memory, a first command received from a host device, the first command executable by one or more processing elements on the processing device, the first command comprising an instruction and associated parameter data, compute a first authentication tag using a cryptographic key associated with the host device, the instruction and at least a portion of the parameter data, and authenticate the first command by comparing the first authentication tag with a second authentication tag computed by the host device and associated with the command.
Inventor(s): Niall MCDONNELL of Limerick (IE) for intel corporation, Ambalavanar ARULAMBALAM of Center Valley PA (US) for intel corporation, Bruce RICHARDSON of Shannon (IE) for intel corporation, Te MA of Allentown PA (US) for intel corporation
IPC Code(s): H04L47/125, H04L47/30, H04L47/625
Abstract: methods, apparatus, and computer programs are disclosed for buffer management in load balancing. in one embodiment, a method is disclosed to comprise providing a set of buffers by a storage of a load balancer to store packets to be distributed by the load balancer, and distributing the packets by the load balancer to a set of cores of a computer processor to be processed by the set of cores. the method further comprises responsive to buffer utilization in the storage over a first threshold, obtaining by circuitry of the load balancer, from top of a memory stack coupled to the storage, additional buffers to store the packets to be distributed and responsive to buffer utilization in the storage below a second threshold, returning by the circuitry of the load balancer, available buffers in the storage to the top of the memory stack.
Inventor(s): Manasi Deval of Portland OR (US) for intel corporation, Gregory Bowers of Hillsboro OR (US) for intel corporation
IPC Code(s): H04L9/40, H04L9/08, H04L69/16, H04L69/164, H04L69/321, H04L69/324
Abstract: technologies for accelerated quic packet processing include a computing device having a network controller. the computing device programs the network controller with an encryption key associated with a quic protocol connection. the computing device may pass a quic packet to the network controller, which encrypts a payload of the quic packet using the encryption key. the network controller may segment the quic packet into multiple segmented quic packets before encryption. the network controller transmits encrypted quic packets to a remote host. the network controller may receive encrypted quic packets from a remote host. the network controller decrypts the encrypted payload of received quic packets and may evaluate an assignment function with an entropy source in the received quic packets and forward the received quic packets to a receive queue based on the assignment function. each receive queue may be associated with a processor core. other embodiments are described and claimed.
Inventor(s): Richard DORRANCE of Hillsboro OR (US) for intel corporation, Ignacio ALVAREZ of Portland OR (US) for intel corporation, Deepak DASALUKUNTE of Beaverton OR (US) for intel corporation, S M Iftekharul ALAM of Hillsboro OR (US) for intel corporation, Sridhar SHARMA of Palo Alto CA (US) for intel corporation, Kathiravetpillai SIVANESAN of Portland OR (US) for intel corporation, David Israel GONZALEZ AGUIRRE of Portland OR (US) for intel corporation, Ranganath KRISHNAN of Hillsboro OR (US) for intel corporation, Satish JHA of Portland OR (US) for intel corporation
IPC Code(s): H04W4/46, G08G1/01, H04W72/04
Abstract: a method for authenticating features reported by a vehicle includes receiving, from a network, a map of an area with confidence weights corresponding to each feature on the map and/or a list of trusted users; upon the vehicle entering the area, checking whether the vehicle is on the list of trusted users; and checking features reported from the vehicle and matching the features to the map of the area.
Inventor(s): Daniel Cohn of Raanana (IL) for intel corporation, David Birnbaum of Modiin (IL) for intel corporation, Ehud Reshef of Qiryat Tivon (IL) for intel corporation, Ofer Hareuveni of Haifa (IL) for intel corporation, Dor Chay of Haifa (IL) for intel corporation
IPC Code(s): H04W28/02, H04W40/12
Abstract: for example, a wireless communication device may be configured to determine a concurrent multiple band (cmb) routing scheme based on quality of service (qos) requirement information and network condition information, the cmb routing scheme to route a plurality of application streams to a plurality of radios of the wireless communication device for wireless communication over a plurality of wireless communication bands, the plurality of application streams corresponding to one or more applications to be executed by the wireless communication device; and to route the plurality of application streams to the plurality of radios by determining, based on the cmb routing scheme, to which radio of the plurality of radios to route the application stream of the plurality of application streams.
Inventor(s): Rafia Malik of Portland OR (US) for intel corporation, Sudeep Palat of Cheltenham (GB) for intel corporation, Yujian Zhang of Beijing (CN) for intel corporation, Marta Martinez Tarradell of Hillsboro OR (US) for intel corporation, Yi Guo of Shanghai (CN) for intel corporation, Youn Hyoung Heo of San Jose CA (US) for intel corporation
IPC Code(s): H04W28/06, H04L47/32, H04W28/02
Abstract: the present disclosure provides various mechanisms to improve the communication of critical data, such as extended reality (xr) data, cloud gaming (cg) data, ultra-reliable low latency communications (urllc) data, internet of things (iot) data, and/or any other type of high priority data/traffic. the described mechanisms include enhancements to buffer status reporting mechanisms; packet, protocol data unit (pdu), and/or service data unit (sdu) discard mechanisms; mechanisms to resolve issues related to system frame number (sfn) wraparound; and network congestion detection mechanisms. other embodiments may be described and/or claimed.
Inventor(s): Salvatore Talarico of Los Gatos CA (US) for intel corporation, Gang Xiong of Beaverton OR (US) for intel corporation, Yingyang Li of Beijing (CN) for intel corporation, Daewon Lee of Portland OR (US) for intel corporation
IPC Code(s): H04W72/21, H04L5/00
Abstract: a user equipment (ue) configured for carrier frequency operations above 52.6 ghz may decode radio-resource control (rrc) signalling received from a gnodeb (gnb) to configure the ue with a number of resource blocks (rbs) (nrb) for a physical uplink control channel (pucch) resource for each of one or more enhanced pucch formats. the one or more enhanced pucch formats may include enhanced pucch format 0, enhanced pucch format 1 and enhanced pucch format 4. the number of rbs may be configurable to be more than one for the enhanced pucch format 0, the enhanced pucch format 1 and the enhanced pucch format 4. the ue may encode an enhanced pucch format for transmission in accordance with one of the enhanced pucch format 0, the enhanced pucch format 1 and the enhanced pucch format 4. the enhanced pucch format may be transmitted to occupy the number of rbs that are configured.
- Intel Corporation
- G06F1/329
- G06F1/3296
- G06F11/34
- Intel corporation
- G06F3/06
- G06F7/544
- G06F30/34
- G06F9/30
- G06F9/38
- G06F9/52
- G06N3/04
- G06N3/063
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- G06F12/0804
- G06F9/4401
- G06F3/16
- G06F9/455
- H04L9/08
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- G06F1/324
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- G06F11/277
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- G06F21/60
- H04L9/40
- H04L67/10
- G06F8/41
- G06F17/15
- G06F18/21
- G06N3/08
- G06T3/4046
- G06N3/098
- G06T1/20
- G06T3/4053
- G06T11/00
- G06T11/20
- G06T7/73
- G06V20/40
- G06V10/774
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- G06V10/82
- G06V40/16
- H01L21/3065
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- H01L21/324
- H01L29/06
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- H01L27/088
- H01L21/02
- H01L21/8234
- H01L29/08
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- H01L29/423
- H01L29/40
- H01L29/778
- H01Q3/26
- H01L23/66
- H03L7/099
- H04B17/10
- G01R21/133
- G01R25/00
- H04B3/06
- H04B17/14
- H04L25/02
- H04L9/06
- H04L9/32
- H04L47/125
- H04L47/30
- H04L47/625
- H04L69/16
- H04L69/164
- H04L69/321
- H04L69/324
- H04W4/46
- G08G1/01
- H04W72/04
- H04W28/02
- H04W40/12
- H04W28/06
- H04L47/32
- H04W72/21
- H04L5/00
