INTERNATIONAL BUSINESS MACHINES CORPORATION patent applications on January 25th, 2024
Patent Applications by INTERNATIONAL BUSINESS MACHINES CORPORATION on January 25th, 2024
INTERNATIONAL BUSINESS MACHINES CORPORATION: 39 patent applications
INTERNATIONAL BUSINESS MACHINES CORPORATION has applied for patents in the areas of H01L43/12 (6), H01L43/02 (6), G06F40/30 (4), H01L43/08 (4), G10L15/26 (4)
With keywords such as: layer, data, memory, based, processor, forming, include, computing, information, and cache in patent application abstracts.
Patent Applications by INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor(s): Yoshifumi Sakamoto of Shiga-ken (JP) for international business machines corporation, Kentaro Aota of Aichi (JP) for international business machines corporation, John Maxwell Cohn of Richmond VT (US) for international business machines corporation, Hardy Groeger of Baden-Wuerttemberg (DE) for international business machines corporation
IPC Code(s): B60W60/00, G08G1/16, G08G1/01, G05D1/00, G06F11/30, G06F11/36
Abstract: a computer implemented method for evaluating autonomous vehicle safety that includes defining criteria for safety of autonomous vehicles in a test space, and dividing the test space into an intended test space and a un-intended test space for the criteria for safety of autonomous vehicles. the intended test space includes characterizations for the autonomous vehicle that can be quantified, and the un-intended test space includes characterizations that are not quantifiable. the method further includes measuring the safety of the autonomous vehicles in the intended test space. the applying the un-intended test space is applied to the intended test space as feedback into the intended test space; and evaluating the intended test space including the feedback from the unintended test space using a combined simulation of peripheral vehicles and autonomous vehicles to provide the evaluation of autonomous vehicle safety.
Inventor(s): Gregory Breyta of San Jose CA (US) for international business machines corporation, Robert David Allen of Golden CO (US) for international business machines corporation, Nitin Shashikant Parekh of Los Altos CA (US) for international business machines corporation
IPC Code(s): C08J11/20
Abstract: a waste polyester material is prepared for recycling by dissolving the material in a solution comprising hexafluoroisopropyl (hfipa) and a chlorinated hydrocarbon, such as dichloromethane (dcm) and/or an aromatic hydrocarbon, such as toluene or xylene, to form a dissolved polyester sample. the dissolved polyester may be prepared for recycling by evaporation, spray drying, and/or precipitation, which produces a purified solid polyester product. the dissolution solution, which is separated from the purified solid polyester product, is also recycled through distillation with purification.
Inventor(s): Tobias Webel of Schwaebisch-Gmuend (DE) for international business machines corporation, Alejandro Alberto Cook Lobo of Stuttgart (DE) for international business machines corporation, Andrew A. Turner of Underhill VT (US) for international business machines corporation, CHRISTIAN JACOBI of West Park NY (US) for international business machines corporation, Eberhard Engler of Tübingen (DE) for international business machines corporation, Edward C. McCain of Lagrangeville NY (US) for international business machines corporation, Kevin P. Low of Poughkeepsie NY (US) for international business machines corporation, Phillip John Restle of Katonah NY (US) for international business machines corporation, Pradeep Bhadravati Parashurama of Bhadravati (IN) for international business machines corporation, Alper Buyuktosunoglu of White Plains NY (US) for international business machines corporation, KARL EVAN SMOCK ANDERSON of Poughkeepsie NY (US) for international business machines corporation, Sean Michael Carey of Dutchess NY (US) for international business machines corporation, KENNEDY CHERUIYOT of Gardiner NY (US) for international business machines corporation, Daniel Kiss of Stuttgart (DE) for international business machines corporation, Isidore G. Bendrihem of Fort Lee NJ (US) for international business machines corporation, Eric Jason Fluhr of Leander TX (US) for international business machines corporation, IAN KRISPIN CARMICHAEL of Round Rock TX (US) for international business machines corporation, Gregory Scott Still of Raleigh NC (US) for international business machines corporation
IPC Code(s): G06F1/28, G06F9/48
Abstract: embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.
Inventor(s): Lu Fu of Ningbo (CN) for international business machines corporation, Jin Shi of Ningbo (CN) for international business machines corporation, Jie Jiang of Ningbo (CN) for international business machines corporation, Wen Juan Nie of Ningbo (CN) for international business machines corporation, Ke Huan Yin of Ningbo (CN) for international business machines corporation
IPC Code(s): G06F3/0489, G06F3/0482
Abstract: according to an exemplary embodiment of the present invention, a method is provided. the method includes identifying ui controls in a gui for display on a screen of a computing device. the method further includes determining a position relationship of the ui controls. the method further includes mapping the ui controls to keyboard areas such that a position relationship of the keyboard areas corresponds with the position relationship of the ui controls. one or more keys within the individual areas are associated with the ui controls that are mapped to the respective keyboard areas.
Inventor(s): Georg Basil Richard Dr Moshous of Unterföhring (DE) for international business machines corporation, Adriana Pellegrini Furnielis of Valinhos (BR) for international business machines corporation, Sarvesh S. Patel of Pune (IN) for international business machines corporation, Marc Henri Coq of Hopewell Junction NY (US) for international business machines corporation, Ebenezer kofi of Duluth GA (US) for international business machines corporation
IPC Code(s): G06F3/06
Abstract: in one general embodiment, a computer-implemented method includes detecting individual sequential input/output (i/o) workloads in a stream of superimposed i/o workloads accessing a same physical volume. the detecting is based on a time dependency corresponding to accesses of blocks of the volume. in another general embodiment, a computer-implemented method includes detecting a plurality of sequential input/output (i/o) workloads in an i/o stream of superimposed workloads accessing a same volume, the detecting being based on a time dependency corresponding to accesses of blocks of the volume. a sequentiality factor is calculated for each of the sequential i/o workloads.
Inventor(s): Noriko Yamamoto of Tokyo (JP) for international business machines corporation, Hiroshi Itagaki of Yokohama (JP) for international business machines corporation, Tsuyoshi Miyamura of Yokohama (JP) for international business machines corporation, Tohru Hasegawa of Tokyo (JP) for international business machines corporation, Shinsuke Mitsuma of Tokyo (JP) for international business machines corporation, Atsushi Abe of Ebina (JP) for international business machines corporation
IPC Code(s): G06F3/06
Abstract: a tool for tape library hierarchical storage management. the tool determines there is available tape capacity on a tape cartridge mounted to a tape drive to migrate data from a migration queue during recall operations. the tool sends a locate end of data (eod) command to the tape drive. the tool determines the migration queue is within a longitudinal position (lpos) range. the tool writes data from the migration queue to the tape cartridge within the lpos range.
Inventor(s): Daniel Waddington of Morgan Hill CA (US) for international business machines corporation, Saransh Gupta of San Jose CA (US) for international business machines corporation
IPC Code(s): G06F9/455
Abstract: an embodiment includes a virtual machine (vm) memory synchronization process for improved failure tolerance. the process includes writing, by an intelligent memory controller (imc), current snapshot data to a first series of contiguous memory addresses, where the current snapshot data is received by the imc from a memory of an active vm via a direct memory access (dma) transfer operation. the imc executes concurrent threads associated with respective spans of the contiguous memory addresses, where the concurrent threads control compression processing of respective portions of the current snapshot data resulting in corresponding portions of processed current snapshot data, where the concurrent threads comprise a thread bound to a hardware accelerator that performs the compression processing of a portion of the current snapshot data. the process then transmits the processed current snapshot data to a standby vm as a current synchronization snapshot of the active vm.
Inventor(s): Vishal Mansur of Bangalore (IN) for international business machines corporation, Sivakumar Krishnasamy of Bangalore (IN) for international business machines corporation, Niranjan Srinivasan of BANGALORE (IN) for international business machines corporation
IPC Code(s): G06F9/455, H04L61/103
Abstract: in an approach to intelligent connection placement across multiple logical ports, a mapping table for a virtual machine is created. responsive to determining that an entry exists in the mapping table for the port on the peer device, whether a virtual function exists the port on the peer device in the mapping table for the same physical function is determined. a virtual function is selected from the mapping table to connect the local port to the port on the peer device.
Inventor(s): Anthony P. PRAINO of Poughquag NY (US) for international business machines corporation, Eli Michael DOW of Pleasant Valley NY (US) for international business machines corporation, Lloyd A. TREINISH of Cortlandt Manor NY (US) for international business machines corporation
IPC Code(s): G06F9/48, G01W1/10
Abstract: a data center management system may predict localized weather conditions for a location of a data center during a period of time. the data center management system may determine whether the localized weather conditions will degrade an operation of the data center during the period of time. the data center management system may obtain computational workload information identifying one or more computational workloads scheduled for execution at the data center during the period of time. the data center management system may determine, based on the computational workload information, one or more priorities associated with the one or more computational workloads. the data center management system may schedule the one or more computational workloads for execution based on the one or more priorities and based on determining whether the localized weather conditions will degrade the operation of the data center.
Inventor(s): Malarvizhi Kandasamy of OMBR Layout (IN) for international business machines corporation, Sudheesh S. Kairali of Kozhikode (IN) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G06F9/50
Abstract: described are techniques for reference implementation of cloud computing resources. the techniques include receiving specifications for a computing resource flow to implement a computing solution in a cloud computing environment. the computing resource flow comprises a set of computing resources and computing resource relationships that implement the computing solution. the techniques further include identifying a reference architecture that corresponds to at least a part of the computing resource flow for the computing solution and obtaining a reference template for the reference architecture from a reference code repository. the techniques further include generating a solution template that is based in part on the reference template, and the solution template provisions the computing resource flow in the cloud computing environment to implement the computing solution.
Inventor(s): Alejandro Alberto Cook Lobo of Stuttgart (DE) for international business machines corporation, Andrew A. Turner of Underhill VT (US) for international business machines corporation, CHRISTIAN JACOBI of West Park NY (US) for international business machines corporation, Eberhard Engler of Tübingen (DE) for international business machines corporation, Edward C. McCain of McCain NY (US) for international business machines corporation, Kevin P. Low of Poughkeepsie NY (US) for international business machines corporation, Phillip John Restle of Katonah NY (US) for international business machines corporation, Pradeep Bhadravati Parashurama of Bhadravati (IN) for international business machines corporation, Tobias Webel of Schwaebisch-Gmuend (DE) for international business machines corporation, Alper Buyuktosunoglu of White Plains NY (US) for international business machines corporation, KARL EVAN SMOCK ANDERSON of Poughkeepsie NY (US) for international business machines corporation, Sean Michael Carey of Dutchess BY (US) for international business machines corporation, KENNEDY CHERUIYOT of Gardiner NY (US) for international business machines corporation, Daniel Kiss of Stuttgart (DE) for international business machines corporation, Isidore G. Bendrihem of Fort Lee NJ (US) for international business machines corporation, IAN KRISPIN CARMICHAEL of Round Rock TX (US) for international business machines corporation
IPC Code(s): G06F11/07, G06F1/30
Abstract: embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. the at least one droop sensor parameters affects a sensitivity to a voltage droop. in response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. it is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.
Inventor(s): Sheng Yan Sun of Beijing (CN) for international business machines corporation, Xiaobo Wang of Beijing (CN) for international business machines corporation, Shuo Li of Beijing (CN) for international business machines corporation, Chun Lei Xu of Xian (CN) for international business machines corporation
IPC Code(s): G06F12/1009, G06F12/0862
Abstract: this disclosure provides a method, a computing system, and a computer program product for managing prefetching of pages in a database system. the method comprises obtaining shared information associated with page access, wherein the shared information associated with the page access includes information associated with the page access from a plurality of computing nodes. the method further comprises determining whether to prefetch a number of pages into a global buffer pool based at least on the shared information associated with the page access using a sequential prefetching method.
Inventor(s): Shakti Kapoor of Austin TX (US) for international business machines corporation, Nelson Wu of Austin TX (US) for international business machines corporation, Manoj Dusanapudi of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F12/0875
Abstract: a processor includes a load and store unit (lsu) and a cache memory, and transfers data information from a store queue in the lsu to the cache memory. the cache memory requests an information packet from the lsu when the cache memory determines that an available entry exists in a store queue within the cache memory. the lsu acknowledges the request and transfers an information packet to the cache memory. the lsu anticipates that an additional available entry exists in the cache memory, transmits an additional acknowledgement to the cache memory, and transfers an additional information packet, before receiving an additional request from the cache memory. the cache memory stores the additional information packet if an additional available entry exists in the cache store queue. the cache memory rejects the additional information packet if no additional available entries exist in the cache store queue. the lsu must then retry the transfer of the additional information packet when the cache memory subsequently requests the additional information packet. the cache memory can set or reset a time delay in requesting a subsequent information packet based on several factors within the cache memory and the processor, including the number of available entries within the cache store queue. a corresponding method and computer program product are also disclosed.
Inventor(s): Abhishek Seth of Deoband (IN) for international business machines corporation, Soma Shekar Naganna of Bangalore (IN) for international business machines corporation, Geetha Sravanthi Pulipaty of Bangalore (IN) for international business machines corporation, Prabhakaran Ramalingam of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F16/215, G06F16/28, G06F16/23
Abstract: a computer-implemented method, system and computer program product for managing relationships between entities in master data management based systems. record level relationships at an entity level are resolved. furthermore, a unified view of relationships between entities is determined using composite rules on the underlying resolved record level relationships. additionally, an anchor member for each linked entity is determined, where the entities are linked together based on the determined unified view of relationships between entities. furthermore, a record transaction involving creating, updating or deleting a record of an entity linked with another entity is received. the relationship between the linked entities is then validated or invalidated based on an impact of the record transaction with the anchor member of one of the linked entities. in this manner, relationships between entities are managed when record transactions involving creating, updating or deleting a record associated with such entities occur.
Inventor(s): Debapriya Chatterjee of Austin TX (US) for international business machines corporation, Christian Zoellin of Bad Urach (DE) for international business machines corporation, Bradly George Frey of Austin TX (US) for international business machines corporation, Brian W. Thompto of Austin TX (US) for international business machines corporation
IPC Code(s): G06F21/74, G06F9/38
Abstract: a computer system, processor, and/or method for changing the mode of operation of a computer without rebooting includes: a processor having a configuration register, the configuration register having a privilege entry (prvs) register field for each of one or more privilege levels, each prvs register field for each privilege level having one or more control aspect entries; and an enforce below (enfb) register field, each enfb register field for each privilege level having one or more control aspect entries, the prvs register field control aspects being equal in number to and corresponding to the enrb register field control aspects. the prvs register fields and the enfb register fields are used to change the processor from a secure mode to a performance mode while running software applications.
Inventor(s): Mukundan Sundararajan of Bangalore (IN) for international business machines corporation, SIDDHARTH K. SARAYA of Raniganj (IN) for international business machines corporation
IPC Code(s): G06F40/205, G06F40/30, G06F40/47
Abstract: according to one embodiment, a method, computer system, and computer program product for coordinating professional language is provided. the present invention may include running, by a processor, at least one professional parsing algorithm and at least one non-professional parsing algorithm on an ingested writing; assigning, by at least one of the professional parsing algorithms and at least one of the non-professional parsing algorithms, one or more initial scores to the ingested writing; determining, by a machine learning model, one or more differences between the ingested writing and stored professional data by comparing the one or more initial scores of the ingested writing to the stored professional data; determining a variation percentage score of the ingested writing based on the differences; and transmitting at least one suggested modification of the ingested writing based on the variation percentage score to a transmitting device.
Inventor(s): Swagath VENKATARAMANI of White Plains NY (US) for international business machines corporation, Vijayalakshmi SRINIVASAN of New York NY (US) for international business machines corporation, Shubham JAIN of Elmsford NY (US) for international business machines corporation, Sarada KRITHIVASAN of Chennai (IN) for international business machines corporation, Sanchari SEN of White Plains NY (US) for international business machines corporation
IPC Code(s): G06N3/08, G06F9/30, G06F9/38
Abstract: embodiments are provided for efficient realization of memory-bound operations in a computing system by a processor. data may be read from and written to a memory at a granular level using a stickification operation. one or more regions of activation and weight tensor data on the memory may be annotated by coupling the stickification operation with padding.
Inventor(s): Benjamin SZNAJDER of Jerusalem (IL) for international business machines corporation, Noam SLONIM of Jerusalem (IL) for international business machines corporation, Eyal SHNARCH of Haifa (IL) for international business machines corporation, Guy LEV of Tel Aviv (IL) for international business machines corporation, Sachindra JOSHI of Gurgaon (IN) for international business machines corporation, Chulaka GUNASEKARA of New Hyde Park NY (US) for international business machines corporation
IPC Code(s): G06N5/02
Abstract: an example system includes a processor to receive unlabeled data, few-shot training data, and a pre-trained model. the processor can split the unlabeled data into a number of groups corresponding to different perspectives. the processor can generate weakly labeled data for each of the number of groups using a respective associated heuristic. the processor can inter-train a model for each different perspective based on respective weakly labeled data. the processor can fine-tune each inter-trained model based on the few-shot training data for each different perspective to generate a final model for each different perspective.
Inventor(s): Tsunehiko Tanaka of Chuo-ku (JP) for international business machines corporation, Daiki Kimura of Midori-ku (JP) for international business machines corporation, Michiaki Tatsubori of Oiso (JP) for international business machines corporation
IPC Code(s): G06N5/04, G06N5/02
Abstract: aspects of the invention include systems and methods configured to extract enriched target-oriented common sense from grounded graphs to support efficient next step decision making of an autonomous agent. a non-limiting example computer-implemented method includes extracting common sense from a source. the extracted common sense can include a first knowledge graph. an environment state can be extracted from an observation. the extracted environment state can include a second knowledge graph. the second knowledge graph can include an interactive object and a state of the interactive object. a difference graph including the extracted common sense and the extracted environment state can be generated. a next action is selected based on the difference graph and the next action is taken by an autonomous agent.
Inventor(s): Andrea Z. GIOVANNINI of Zurich (CH) for international business machines corporation, Florian D. GRAF of Zurich (CH) for international business machines corporation, Markus PELNAR of Winterthur (CH) for international business machines corporation, Stefan M. RAVIZZA of Wallisellen (CH) for international business machines corporation
IPC Code(s): G06N5/04, G06F16/901, G06F40/30, G10L15/26
Abstract: original idea extraction from written data is provided by capturing expression as written text data, obtaining a knowledge graph representing concepts and relationships between the concepts, automatically topic modeling the written text data to ascertain thought units and identify respective concepts of the thought unit, mapping a thought unit to the knowledge graph, determining that the thought unit is an original idea, and based on determining that the thought unit is an original idea, storing a representation of the original idea to an idea repository and invoking processing of at least one computer.
Inventor(s): Ismail Yunus Akhalwaya of Emmarentia (ZA) for international business machines corporation, Shashanka Ubaru of Ossining NY (US) for international business machines corporation, Kenneth Lee Clarkson of Madison NJ (US) for international business machines corporation, Mark S. Squillante of Greenwich CT (US) for international business machines corporation, Vasileios Kalantzis of White Plains NY (US) for international business machines corporation, Lior Horesh of North Salem NY (US) for international business machines corporation
IPC Code(s): G06N10/40, G06N10/20
Abstract: a quantum computer-implemented system, method, and computer program product for quantum topological domain analysis (qtda). the qtda method achieves an improved exponential speedup and depth complexity of o(n log(1/(�∈))) where n is the number of data points, ∈ is the error tolerance, � is the smallest nonzero eigenvalue of the restricted laplacian, and achieves quantum advantage on general classical data. the qtda system and method efficiently realizes a combinatorial laplacian as a sum of pauli operators; performs a quantum rejection sampling and projection approach to build the relevant simplicial complex repeatedly and restrict the superposition to the simplices of a desired order in the complex; and estimates betti numbers using a stochastic trace/rank estimation method that does not require quantum phase estimation. the quantum circuit and qtda method exhibits computational time and depth complexities for betti number estimation up to an error tolerance ∈.
Inventor(s): Giulio Zizzo of Dublin (IE) for international business machines corporation, Ambrish Rawat of Dublin (IE) for international business machines corporation, Naoise Holohan of Maynooth (IE) for international business machines corporation, Seshu Tirupathi of Dublin (IE) for international business machines corporation
IPC Code(s): G06N20/00
Abstract: the present disclosure relates to a method comprising at training system iteratively training a machine learning algorithm using current training data. the current training data comprises a local dataset of a current task and a replay dataset and may be updated for a next iteration as follows. a training dataset may be received. if the training dataset is not s shared dataset and its task is different from the current task: information representing the local dataset may be shared with other training systems, the local dataset may be added to the replay dataset, and the received training dataset may be used as the local dataset for a next iteration. in case the task is the current task: the received training dataset may be added to the local dataset. if the training dataset is a shared dataset, the received training dataset may be added to the replay dataset.
Inventor(s): Itzhack Goldberg of Hadera (IL) for international business machines corporation, Rick A. Hamilton, II of Charlottesville VA (US) for international business machines corporation, Shawn P. Mullen of Buda TX (US) for international business machines corporation, Clifford A. Pickover of Yorktown Heights NY (US) for international business machines corporation
IPC Code(s): G06Q20/40, G06Q20/34, G06F16/22, G06Q20/10
Abstract: a method for establishing an index of usability associated with a replacement payment card is provided. the method may include receiving a payment card replacement request in a vending facility. the method may further include identifying at least one possible risk factor associated with a user utilizing the replacement payment card. the method may also include creating a risk assessment based on the at least one identified possible risk factor. the method may further include establishing an index of usability for the replacement payment card based on the created assessment, whereby a value of the index of usability correlates to a plurality of restrictions placed on using the replacement payment card. the method may also include storing the established index of usability in a database.
Inventor(s): Aaron K. Baughman of Cary NC (US) for international business machines corporation, Eduardo Morales of KEY BISCAYNE FL (US) for international business machines corporation, Micah Forster of Round Rock TX (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G06T19/00, G06N10/80, G06V20/40, G06T15/10, G06V20/20
Abstract: an embodiment includes accessing captured video of a first physical object in a physical environment. the embodiment also includes detecting a feature of the first physical object in a first frame of the video. the embodiment encodes a first qubit with a first quantum state based on a first value of the feature of the first physical object, and then entangles the first qubit with a second qubit forming an entangled qubit pair. the embodiment detects a second quantum state of the second qubit of the entangled qubit pair and renders computer-generated content of a virtual environment that includes a computer-generated first virtual object that corresponds to the first physical object, where the rendering comprises determining a property of the first virtual object based on the detected second quantum state.
Inventor(s): Andrew R. Freed of Cary NC (US) for international business machines corporation, Robert Michael Hervey of Apex NC (US) for international business machines corporation, Sorabh Murgai of Cary NC (US) for international business machines corporation
IPC Code(s): G10L15/02, G10L15/26
Abstract: a method for speech recognition using cadence patterns is provided. the method includes identifying speech cadence in user speech, which includes a plurality of sounds and pauses. at least one speech cadence pattern is identified from the plurality of sounds and pauses. the user speech is transcribed, and the transcribed user speech is modified based on the identified speech cadence pattern.
Inventor(s): Ravi Nair of Briarcliff Manor NY (US) for international business machines corporation, Swagath Venkataramani of White Plains NY (US) for international business machines corporation, Vijayalakshmi Srinivasan of New York NY (US) for international business machines corporation, Arvind Kumar of Chappaqua NY (US) for international business machines corporation
IPC Code(s): G11C11/4096, G11C11/4093, G11C5/06
Abstract: a memory system, a method of assembling the memory system, and a computer system. the memory system includes a global memory device coupled to a plurality of processing elements. the global memory device is positioned external to a chip on which the plurality of processing devices reside. the memory system also includes at least one main scratchpad coupled to the at least one processing element of the plurality of processing devices and the global memory device. the memory system further includes a plurality of auxiliary scratchpads coupled to the plurality of processing elements and the global memory device. the one or more auxiliary scratchpads are configured to store static tensors. at least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device.
Inventor(s): Ghazi Sarwat Syed of Zurich (CH) for international business machines corporation, Abu Sebastian of Adliswil (CH) for international business machines corporation
IPC Code(s): G11C13/00
Abstract: the invention is notably directed to a device comprising a plurality of resistive memory elements. the plurality of resistive memory elements comprises a resistive material. the device is configured to apply programming pulses to a subset of the plurality of resistive memory elements to perform a temporary resistance change of the resistive material of the subset for a predefined retention period, thereby programming the subset of the plurality of resistive elements from a first resistance state corresponding to a first binary state to a second resistance state corresponding to a second binary state. the device is configured such that a resistance of the subset of the plurality of resistive elements reverts automatically during the predefined retention period from the second resistance state to the first resistance state by an inherent material property of the resistive material, thereby automatically deleting the second binary state.
Inventor(s): Ted Thorbeck of Elmsford NY (US) for international business machines corporation, Corrado P. Mancini of Hopewell Junction NY (US) for international business machines corporation
IPC Code(s): H01F19/00, H01L39/22, H01L39/02, G06N10/00
Abstract: a traveling wave parametric amplifier (twpa) transmission line with improved bandwidth includes one or more unit cell. each unit cell includes a capacitor to a ground and a josephson junction in series configured to provide inductance and non-linearity. one or more dispersion resonator is coupled to the transmission line. the dispersion resonator is configured to (i) use a first harmonic mode of the resonator for resonant phase matching in the transmission line and (ii) prevent a second mode of the resonator from interacting with an intermodulation product of the transmission line.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, HUIMEI ZHOU of Albany NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Kisik Choi of Watervliet NY (US) for international business machines corporation
IPC Code(s): H01L23/535, H01L27/12, H01L23/522, H01L21/74
Abstract: a buried power rail is provided in a non-active device region. the buried power rail includes a dielectric liner located on a lower portion of a sidewall and a bottommost surface of the buried power rail. a dielectric cap is located on an upper portion of the sidewall of the buried power rail as well as on a topmost surface of the buried power rail. the dielectric cap is present during the fabrication of a functional gate structure and thus the problems associated with prior art buried power rails are circumvented. the dielectric cap can be removed after the functional gate structure has been formed and a via to buried power rail (vbpr) contact structure can be formed in contact with the buried power rail. in some applications, and after a gate cut process, a gate cut dielectric structure can be formed in contact with the dielectric cap.
Inventor(s): Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation, Daniel Schmidt of Niskayuna NY (US) for international business machines corporation, Alexander Reznicek of Troy NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L29/66, H01L21/8238, H01L27/092
Abstract: embodiments of present invention provide a method of forming a semiconductor structure. the method includes forming a first set of nanosheets and a second set of nanosheets on top of the first set of nanosheets, wherein the first set of nanosheets has an uppermost nanosheet and the second set of nanosheets has a lowermost nanosheet, the lowermost nanosheet being separated from the uppermost nanosheet by a first gap; forming a conformal liner covering the first set of nanosheets and the first gap; covering a first portion of the conformal liner at the first gap with a protective stud; selectively removing a second portion of the conformal liner from end surfaces of the first set of nanosheets; and forming source/drain at the end surfaces of the first set of nanosheets. a structure formed thereby is also provided.
Inventor(s): John S. Werner of Fishkill NY (US) for international business machines corporation, Noah Singer of White Plains NY (US) for international business machines corporation, John Torok of Poughkeepsie NY (US) for international business machines corporation, Arkadiy O. Tsfasman of Wappingers Falls NY (US) for international business machines corporation
IPC Code(s): H01M10/613, H01M10/627, H01M10/63, H01M10/6552, H01M10/6563, H01M10/6568, H01M10/667, A62C3/16
Abstract: an apparatus for a fire suppressant system on a server rack includes an integrated battery feature, a manifold, a conduit, and a control card, where the integrated battery feature includes a plurality of battery cells in an enclosure. a first end of the conduit coupled to a control valve on the manifold and a second end of the conduit coupled to the integrated battery feature. the control card configured to open the control valve on the manifold, where the control valve is configured to release a fire suppressant into the enclosure of the integrated battery feature. in one embodiment, the fire suppressant is contained within a pressurized fire suppressant reservoir mounted on the server rack. in another embodiment, the fire suppressant is a cooling fluid diverted from a radiator cooling unit on the server rack.
Inventor(s): Matthew Beck of Danbury CT (US) for international business machines corporation
IPC Code(s): H03K17/92, H03K3/01
Abstract: a method of using josephson junctions to convert the envelope of radio-frequency signals into baseband control pulses includes injecting a biasing current into an envelope detector circuit. the biasing current is identified based on first and second critical currents of superconducting devices in the envelope detector circuit. the first critical current corresponds to the envelope detector circuit receiving no rf signals. the second critical current corresponds to the envelope detector circuit receiving maximum rf signals. the method further includes receiving a modulated radio frequency (rf) signal at the envelope detector circuit to detect an envelope of the received rf signal. the output of the envelope detector circuit is used to drive an output load. the output is generated based on the detected envelope by the envelope detector circuit.
20240031305.PROACTIVE AUTO-SCALING_simplified_abstract_(international business machines corporation)
Inventor(s): Yi Ming Wang of Xi'an (CN) for international business machines corporation, Rui Wang of Beijing (CN) for international business machines corporation, Jing Bo Jiang of Beijing (CN) for international business machines corporation, Yan Liu of Beijing (CN) for international business machines corporation
IPC Code(s): H04L47/78, H04L47/70, H04L47/80, H04L47/762
Abstract: in an approach for proactive service group based auto-scaling, a processor collects usage data generated in one or more services in a container platform. a processor predicts access situation and resource utilization of the one or more services based on the usage data. a processor constructs a dynamic correlation topology among the one or more services based on the access situation and resource utilization. a processor identifies associated services correlated with the one or more services based on the dynamic correlation topology. a processor, in response to a service request exceeding a pre-set threshold, expands the one or more services and associated services.
Inventor(s): Lisa Seacat DeLuca of Bozeman MT (US) for international business machines corporation, Jeremy A. Greenberger of San Jose CA (US) for international business machines corporation, David M. Ogle of Powell OH (US) for international business machines corporation
IPC Code(s): H04M3/22, H04L9/40, H04W12/06, H04M3/51
Abstract: according to one embodiment, a method, computer system, and computer program product for processing a secure data phone request are provided. the embodiment may include identifying a user participating in a voice call by a user voice signature. the embodiment may also include identifying a verbal request, received during the voice call, for the identified user to provide sensitive information. the embodiment may further include identifying, upon authorization of the identified user, a response from a repository of stored, pre-recorded responses associated with the identified user that satisfies the request, where the stored responses are stored as a pre-recorded voice clip or a pre-recorded number sequence on the client computing device.
Inventor(s): Aaron K. Baughman of Cary NC (US) for international business machines corporation, Micah Forster of Round Rock TX (US) for international business machines corporation, Ashafaaq Minhas of Jersey City NJ (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): H04N5/272, H04N13/117, H04N13/243
Abstract: video of a plurality of fields of view of a scene is captured, each field of view comprising data of the scene from a different vantage point. an excitement level is determined by analyzing a portion of the captured video. using the excitement level, a time series of future excitement levels is forecast. using the time series of future excitement levels, a virtual field of view path of the scene is forecast. an insert image is determined to be included in the virtual field of view path. captured data from at least two video cameras in the plurality of video cameras is composited into a virtual field of view of the scene. a rendering of the insert image is inserted into the virtual field of view.
Inventor(s): Adam Spiegelman of The Hills TX (US) for international business machines corporation, Kevin O'Connell of Mantorville MN (US) for international business machines corporation, Kenneth E. Lubahn of Oronoco MN (US) for international business machines corporation, Justin Christopher Rogers of Rochester MN (US) for international business machines corporation, Eric J. Campbell of Rochester MN (US) for international business machines corporation
IPC Code(s): H05K5/02, E05C19/06, E05C5/02, E05C3/14
Abstract: a latch mechanism includes a mounting bracket, a stop connected to the mounting bracket, a first spring connected to the mounting bracket and in contact with the stop to preload the first spring, and a latch. the latch includes a second spring rotatably connected to the mounting bracket, and a body connected to the second spring. the body includes a pad at one end of the body, and a first pawl at a second end of the body opposite of the pad.
Inventor(s): Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Oscar van der Straten of Guilderland Center NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L43/08, H01L27/22, H01L43/02, H01L43/12, G11C11/16
Abstract: embodiments of present invention provide a method of forming a mram structure. the method includes patterning a bottom electrode layer and a first ferromagnetic layer on top of the bottom electrode layer; depositing a dielectric layer, the dielectric layer covering the bottom electrode layer and the first ferromagnetic layer; creating an opening in the dielectric layer, the opening exposing a portion of the first ferromagnetic layer; forming a tunnel barrier layer inside the opening; forming a second ferromagnetic layer on top of the tunnel barrier layer; patterning the tunnel barrier layer and the second ferromagnetic layer; and forming a top electrode layer on top of the second ferromagnetic layer. structures formed thereby are also provided.
20240032436.MRAM DEVICE STRUCTURE_simplified_abstract_(international business machines corporation)
Inventor(s): Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Oscar van der Straten of Guilderland Center NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L43/08, H01L27/22, H01L43/02, H01L43/12
Abstract: embodiments of present invention provide a method of forming a mram structure. the method includes forming a magnetic tunnel junction (mtj) stack; forming a first dielectric layer to a level above a tunnel barrier layer of the mtj stack, the first dielectric layer partially covering the mtj stack with a top surface of the mtj stack being exposed; depositing an etch-stop layer covering the top surface of the mtj stack and a top surface of the first dielectric layer; depositing a second dielectric layer covering the etch-stop layer; forming an opening in the second dielectric layer; removing a portion of the etch-stop layer above the top surface of the mtj stack; and forming a top contact by depositing a conductive material in the opening. an mram structure formed thereby is also provided.
Inventor(s): Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Oscar van der Straten of Guilderland Center NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation
IPC Code(s): H01L43/02, H01L27/22, H01L43/12
Abstract: embodiments of present invention provide a method of forming a mram structure. the method includes forming a bottom electrode layer surrounded by a bottom dielectric layer; forming an etch-stop layer on top of the bottom electrode layer and the bottom dielectric layer; creating an opening in the etch-stop layer to expose a top surface of the bottom electrode layer; forming a first ferromagnetic layer on top of the bottom electrode layer and the etch-stop layer, with a portion of the first ferromagnetic layer filling the opening in the etch-stop layer; forming a tunnel barrier layer and a second ferromagnetic layer on top of the first ferromagnetic layer; patterning the second ferromagnetic layer, the tunnel barrier layer, and the first ferromagnetic layer; and forming a top electrode layer on top of the second ferromagnetic layer. a structure formed thereby is also provided.
INTERNATIONAL BUSINESS MACHINES CORPORATION patent applications on January 25th, 2024
- INTERNATIONAL BUSINESS MACHINES CORPORATION
- B60W60/00
- G08G1/16
- G08G1/01
- G05D1/00
- G06F11/30
- G06F11/36
- International business machines corporation
- C08J11/20
- G06F1/28
- G06F9/48
- G06F3/0489
- G06F3/0482
- G06F3/06
- G06F9/455
- H04L61/103
- G01W1/10
- G06F9/50
- G06F11/07
- G06F1/30
- G06F12/1009
- G06F12/0862
- G06F12/0875
- G06F16/215
- G06F16/28
- G06F16/23
- G06F21/74
- G06F9/38
- G06F40/205
- G06F40/30
- G06F40/47
- G06N3/08
- G06F9/30
- G06N5/02
- G06N5/04
- G06F16/901
- G10L15/26
- G06N10/40
- G06N10/20
- G06N20/00
- G06Q20/40
- G06Q20/34
- G06F16/22
- G06Q20/10
- G06T19/00
- G06N10/80
- G06V20/40
- G06T15/10
- G06V20/20
- G10L15/02
- G11C11/4096
- G11C11/4093
- G11C5/06
- G11C13/00
- H01F19/00
- H01L39/22
- H01L39/02
- G06N10/00
- H01L23/535
- H01L27/12
- H01L23/522
- H01L21/74
- H01L29/06
- H01L29/66
- H01L21/8238
- H01L27/092
- H01M10/613
- H01M10/627
- H01M10/63
- H01M10/6552
- H01M10/6563
- H01M10/6568
- H01M10/667
- A62C3/16
- H03K17/92
- H03K3/01
- H04L47/78
- H04L47/70
- H04L47/80
- H04L47/762
- H04M3/22
- H04L9/40
- H04W12/06
- H04M3/51
- H04N5/272
- H04N13/117
- H04N13/243
- H05K5/02
- E05C19/06
- E05C5/02
- E05C3/14
- H01L43/08
- H01L27/22
- H01L43/02
- H01L43/12
- G11C11/16
