INTEL CORPORATION patent applications on February 8th, 2024
Patent Applications by INTEL CORPORATION on February 8th, 2024
INTEL CORPORATION: 42 patent applications
INTEL CORPORATION has applied for patents in the areas of G06F9/30 (13), G06F9/30145 (7), G06F9/38 (6), G06F9/3001 (6), G06F9/50 (6)
With keywords such as: data, circuitry, source, element, packed, execution, operand, instruction, processor, and opcode in patent application abstracts.
Patent Applications by INTEL CORPORATION
Inventor(s): Jianfang Zhu of Portland OR (US) for intel corporation, Deepak Samuel Kirubakaran of Hillsboro OR (US) for intel corporation, Raoul Rivas Toledano of Hillsboro OR (US) for intel corporation, Chee Lim Nge of Beaverton OR (US) for intel corporation, Rajshree Chabukswar of Sunnyvale CA (US) for intel corporation, James Hermerding, II of Vancouver WA (US) for intel corporation, Sudheer Nair of Portland OR (US) for intel corporation, William Braun of Beaverton OR (US) for intel corporation, Zhongsheng Wang of Camas WA (US) for intel corporation, Russell Fenger of Beaverton OR (US) for intel corporation, Udayan Kapaley of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F1/329, G06F1/3228, G06F9/38, G06F9/48
Abstract: in one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. the power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. other embodiments are described and claimed.
Inventor(s): Alexander Heinecke of San Jose CA (US) for intel corporation, Menachem Adelman of Modi'in (IL) for intel corporation, Evangelos Georganas of San Jose CA (US) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation, Christopher Hughes of Santa Clara CA (US) for intel corporation, Naveen Mellempudi of Bangalore (IN) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation, Uri Sherman of Bustan Hagalil (IL) for intel corporation, Zeev Sperber of Zikhron Yaakov (IL) for intel corporation
IPC Code(s): G06F7/483
Abstract: techniques for performing arithmetic operations on fp8 values are described. an exemplary instruction includes fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of location of a packed data destination operand, wherein the opcode is to indicate an arithmetic operation execution circuitry is to perform, for each data element position of the identified packed data source operands, the arithmetic operation on fp8 data elements in that data element position in fp8 format and store a result of each arithmetic operation into a corresponding data element position of the identified packed data destination operand.
20240045677.INSTRUCTIONS TO CONVERT FROM FP16 TO FP8_simplified_abstract_(intel corporation)
Inventor(s): Alexander Heinecke of San Jose CA (US) for intel corporation, Menachem Adelman of Modi?in (IL) for intel corporation, Mark Charney of Lexington MA (US) for intel corporation, Evangelos Georganas of San Jose CA (US) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation, Christopher Hughes of Santa Clara CA (US) for intel corporation, Naveen Mellempudi of Bangalore (IN) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation, Uri Sherman of Bustan Hagalil (IL) for intel corporation, Zeev Sperber of Zikhron Yaakov (IL) for intel corporation, Robert Valentine of Kiryat Tivon (IL) for intel corporation
IPC Code(s): G06F9/30
Abstract: techniques for converting fp16 or fp32 data elements to fp8 data elements using a single instruction are described. an exemplary apparatus includes decoder circuitry to decode a single instruction, the single instruction to include a one or more fields to identify a source operand, one or more fields to identify a destination operand, and one or more fields for an opcode, the opcode to indicate that execution circuitry is to convert packed half-precision floating-point data or single-precision floating point data from the identified source to packed fp8 data and store the packed bfloat8 data into corresponding data element positions of the identified destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision floating-point data or single-precision floating point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions.
20240045681.8-BIT FLOATING POINT COMPARISON INSTRUCTIONS_simplified_abstract_(intel corporation)
Inventor(s): Alexander Heinecke of San Jose CA (US) for intel corporation, Menachem Adelman of Modi'in (IL) for intel corporation, Evangelos Georganas of San Jose CA (US) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation, Christopher Hughes of Santa Clara CA (US) for intel corporation, Naveen Mellempudi of Bangalore (IN) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation, Uri Sherman of Bustan Hagalil (IL) for intel corporation, Zeev Sperber of Zikhron Yaakov (IL) for intel corporation
IPC Code(s): G06F9/30
Abstract: techniques for comparing fp8 data elements are described. an exemplary fp8 comparison instruction includes fields for an opcode, an identification of a location of a first packed data source operand, and an identification of a location of a second packed data source operand, wherein the opcode is to indicate that execution circuitry is to perform, for a particular data element position of the packed data source operands, a comparison of a data element at that position, and update a flags register based on the comparison.
Inventor(s): Alexander Heinecke of San Jose CA (US) for intel corporation, Menachem Adelman of Modi'in (IL) for intel corporation, Evangelos Georganas of San Jose CA (US) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation, Christopher Hughes of Santa Clara CA (US) for intel corporation, Naveen Mellempudi of Bangalore (IN) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation, Uri Sherman of Bustan Hagalil (IL) for intel corporation, Zeev Sperber of Zikhron Yaakov (IL) for intel corporation
IPC Code(s): G06F9/30
Abstract: techniques for scale and reduction of fp8 data elements are described. an exemplary instruction includes fields for an having fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operands, a floating point scale operation of a fp8 data element of the first packed data source by multiplying the data element by a power of 2 value, wherein a value of the exponent of the power of 2 value is a floor value of a fp8 data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand.
Inventor(s): Alexander Heinecke of San Jose CA (US) for intel corporation, Menachem Adelman of Modi'in (IL) for intel corporation, Evangelos Georganas of San Jose CA (US) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation, Christopher Hughes of Santa Clara CA (US) for intel corporation, Naveen Mellempudi of Bangalore (IN) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation, Uri Sherman of Bustan Hagalil (IL) for intel corporation, Zeev Sperber of Zikhron Yaakov (IL) for intel corporation
IPC Code(s): G06F9/30
Abstract: techniques for performing square root or reciprocal square root calculations on fp8 data elements in response to an instruction are described. an example of an instruction is one that includes fields for an opcode, an identification of a location of a packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operand, a calculation of a square root value of a fp8 data element in that position and store a result of each square root into a corresponding data element position of the packed data destination operand.
20240045684.INSTRUCTIONS TO CONVERT FROM FP16 TO FP8_simplified_abstract_(intel corporation)
Inventor(s): Alexander Heinecke of San Jose CA (US) for intel corporation, Menachem Adelman of Modi'in (IL) for intel corporation, Mark Charney of Lexington MA (US) for intel corporation, Evangelos Georganas of San Jose CA (US) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation, Christopher Hughes of Santa Clara CA (US) for intel corporation, Naveen Mellempudi of Bangalore (IN) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation, Uri Sherman of Bustan Hagalil (IL) for intel corporation, Zeev Sperber of Zikhron Yaakov (IL) for intel corporation, Robert Valentine of Kiryat Tivon (IL) for intel corporation
IPC Code(s): G06F9/30
Abstract: techniques for converting fp16 to bf8 using bias are described. an example embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed fp8 data using bias terms from the identified source/destination operand and store the packed fp8 data into corresponding data element positions of the identified source/destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed fp8 data using bias terms from the identified source/destination operand and store the packed fp8 data into corresponding data element positions of the identified source/destination operand.
Inventor(s): Menachem Adelman of Modi'in (IL) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation, Alexander Heinecke of San Jose CA (US) for intel corporation, Christopher Hughes of Santa Clara CA (US) for intel corporation, Naveen Mellempudi of Bangalore (IN) for intel corporation, Shahar Mizrahi of Haifa (IL) for intel corporation, Dana Rip of Haifa (IL) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation, Uri Sherman of Bustan Hagalil (IL) for intel corporation, Guy Boudoukh of Ramat Hasharon (IL) for intel corporation, Evangelos Georganas of San Jose CA (US) for intel corporation, Nilesh Jain of Portland OR (US) for intel corporation, Barukh Ziv of Haifa (IL) for intel corporation
IPC Code(s): G06F9/30
Abstract: systems, methods, and apparatuses relating sparsity based fma. in some examples, an instance of a single fma instruction has one or more fields for an opcode, one or more fields to identify a source/destination matrix operand, one or more fields to identify a first plurality of source matrix operands, one or more fields to identify a second plurality of matrix operands, wherein the opcode is to indicate that execution circuitry is to select a proper subset of fp8 data elements from the first plurality of source matrix operands based on sparsity controls from a first matrix operand of the second plurality of matrix operands and perform a fma.
20240045686.INSTRUCTIONS TO CONVERT FROM FP8_simplified_abstract_(intel corporation)
Inventor(s): Alexander Heinecke of San Jose CA (US) for intel corporation, Menachem Adelman of Modi'in (IL) for intel corporation, Evangelos Georganas of San Jose CA (US) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation, Christopher Hughes of Santa Clara CA (US) for intel corporation, Naveen Mellempudi of Bangalore (IN) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation, Uri Sherman of Bustan Hagalil (IL) for intel corporation, Zeev Sperber of Zikhron Yaakov (IL) for intel corporation
IPC Code(s): G06F9/30
Abstract: techniques for converting fp8 data elements to fp16 or fp32 data elements using a single instruction are described. an example apparatus includes decoder circuitry to decode a single instruction, the single instruction to indicate that execution circuitry is to convert packed fp8 data from the identified source to packed half-precision floating-point data or single-precision floating point data and store the packed half-precision floating-point data or single-precision floating point data into corresponding data element positions of the identified destination operand.
Inventor(s): Alexander Heinecke of San Jose CA (US) for intel corporation, Menachem Adelman of Modi'in (IL) for intel corporation, Evangelos Georganas of San Jose CA (US) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation, Christopher Hughes of Santa Clara CA (US) for intel corporation, Naveen Mellempudi of Bangalore (IN) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation, Uri Sherman of Bustan Hagalil (IL) for intel corporation, Zeev Sperber of Zikhron Yaakov (IL) for intel corporation
IPC Code(s): G06F9/30
Abstract: techniques for fp8 classification or manipulation using single instructions are described. an exemplary instruction includes fields for an opcode, an identification of a location of a packed data source operand, an indication of one or more classification checks to perform, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operand, a classification according to the indicated one or more classification checks and store a result of the classification in a corresponding data element position of the destination operand.
20240045688.8-BIT FLOATING POINT FUSED MULTIPLY INSTRUCTIONS_simplified_abstract_(intel corporation)
Inventor(s): Alexander Heinecke of San Jose CA (US) for intel corporation, Menachem Adelman of Modi'in (IL) for intel corporation, Evangelos Georganas of San Jose CA (US) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation, Christopher Hughes of Santa Clara CA (US) for intel corporation, Naveen Mellempudi of Bangalore (IN) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation, Uri Sherman of Bustan Hagalil (IL) for intel corporation, Zeev Sperber of Zikhron Yaakov (IL) for intel corporation
IPC Code(s): G06F9/30, G06F7/487
Abstract: techniques for performing fp8 fma in response to an instruction are described. in some examples, an instruction has fields for an opcode, an identification of location of a packed data source/destination operand (a first source), an identification of a location of a second packed data source operand, an identification of a location of a third packed data source operand, and an identification of location of a packed data source/destination operand, wherein the opcode is to indicate operand ordering and that execution circuitry is to, per data element position, perform a fp8 value fused multiply-accumulate operation using the first, second, and third source operands and store a result in a corresponding data element position of the source/destination operand, wherein the fp8 value has an 8-bit floating point format that comprises one bit for a sign, at least 4 bits for an exponent, and at least two bits for a fraction.
Inventor(s): Alexander Heinecke of San Jose CA (US) for intel corporation, Menachem Adelman of Modi'in (IL) for intel corporation, Evangelos Georganas of San Jose CA (US) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation, Christopher Hughes of Santa Clara CA (US) for intel corporation, Naveen Mellempudi of Bangalore (IN) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation, Uri Sherman of Bustan Hagalil (IL) for intel corporation, Zeev Sperber of Zikhron Yaakov (IL) for intel corporation
IPC Code(s): G06F9/30, G06F7/487, G06F17/16, G06F9/38
Abstract: disclosed embodiments relate to systems and methods for performing 8-bit floating-point vector dot product instructions. in one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of first source, second source, and destination vectors, the opcode to indicate execution circuitry is to multiply pairs of 8-bit floating-point formatted elements of the specified first and second sources, and accumulate the resulting products with previous contents of a corresponding single-precision element of the specified destination, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.
Inventor(s): Dan BAUM of Haifa (IL) for intel corporation, Michael ESPIG of Newberg OR (US) for intel corporation, James GUILFORD of Northborough MA (US) for intel corporation, Wajdi K. FEGHALI of Boston MA (US) for intel corporation, Raanan SADE of Portland OR (US) for intel corporation, Christopher J. HUGHES of Santa Clara CA (US) for intel corporation, Robert VALENTINE of Kiryat Tivon (IL) for intel corporation, Bret TOLL of Hillsboro OR (US) for intel corporation, Elmoustapha OULD-AHMED-VALL of Gilbert AZ (US) for intel corporation, Mark J. CHARNEY of Lexington MA (US) for intel corporation, Vinodh GOPAL of Westborough MA (US) for intel corporation, Ronen ZOHAR of Sunnyvale CA (US) for intel corporation, Alexander F. HEINECKE of San Jose CA (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/38
Abstract: disclosed embodiments relate to matrix compress/decompress instructions. in one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.
Inventor(s): Naveen Mellempudi of Bangalore (IN) for intel corporation, Menachem Adelman of Modi'in (IL) for intel corporation, Evangelos Georganas of San Jose CA (US) for intel corporation, Amit Gradstein of Binyamina (IL) for intel corporation, Christopher Hughes of Santa Clara CA (US) for intel corporation, Alexander Heinecke of San Jose CA (US) for intel corporation, Simon Rubanovich of Haifa (IL) for intel corporation, Uri Sherman of Bustan Hagalil (IL) for intel corporation, Zeev Sperber of Zikhron Yaakov (IL) for intel corporation
IPC Code(s): G06F9/38, G06F7/487, G06F17/16, G06F9/30
Abstract: systems, methods, and apparatuses relating to 8-bit floating-point matrix dot product instructions are described. a processor embodiment includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a destination matrix having single-precision elements, a first source matrix, and a second source matrix, the source matrices having elements that each comprise a quadruple of 8-bit floating-point values, the opcode to indicate execution circuitry is to cause, for each element of the first source matrix and corresponding element of the second source matrix, a conversion of the 8-bit floating-point values to single-precision values, a multiplication of different pairs of converted single-precision values to generate plurality of results, and an accumulation of the results with previous contents of a corresponding element of the destination matrix, decode circuitry to decode the fetched instruction, and the execution circuitry to respond to the decoded instruction as specified by the opcode.
Inventor(s): Prashant CHAUDHARI of Folsom CA (US) for intel corporation, Gregory BERGSCHNEIDER of Frederick CO (US) for intel corporation
IPC Code(s): G06F9/455
Abstract: apparatus and method for concurrent performance monitoring. for example, one embodiment of an apparatus comprises: compute hardware logic comprising parallel execution resources to concurrently execute a number of workloads; virtualization hardware logic to allocate the parallel execution resources between a number of virtual machines, each virtual machine to execute a workload on its allocated portion of the execution resources concurrently with workloads executed by one or more other virtual machines executed on corresponding other allocated portions of the execution resources; and programmable performance monitoring circuitry to be dynamically partitioned based on the number of virtual machines and the portion of the execution resources allocated to each virtual machine, the programmable performance monitoring circuitry to differentiate between performance monitoring data of different virtual machines based on one or more unique identifiers associated with each of the allocated portions of execution resources.
Inventor(s): Ravi L. Sahita of Portland OR (US) for intel corporation, Tin-Cheung Kung of Folsom CA (US) for intel corporation, Vedvyas Shanbhogue of Austin TX (US) for intel corporation, Barry E. Huntley of Hillsboro OR (US) for intel corporation, Arie Aharon of Haifa (IL) for intel corporation
IPC Code(s): G06F9/455, H04L9/06, G06F9/50
Abstract: implementations describe a computing system that implements a plurality of virtual machines inside a trust domain (td), enabled via a secure arbitration mode (seam) of the processor. a processor includes one or more registers to store a seam range of memory, a td key identifier of a td private encryption key. the processor is capable of initializing a trust domain resource manager (tdrm) to manage the td, and a virtual machine monitor within the td to manage the plurality of virtual machines therein. the processor is further capable of exclusively associating a plurality of memory pages with the td, wherein the plurality of memory pages associated with the td is encrypted with a td private encryption key inaccessible to the tdrm. the processor is further capable of using the seam range of memory, inaccessible to the tdrm, to provide isolation between the tdrm and the plurality of virtual machines.
Inventor(s): Deepak Dasalukunte of Beaverton OR (US) for intel corporation, Richard Dorrance of Hillsboro OR (US) for intel corporation, Renzhi Liu of Portland OR (US) for intel corporation, Henchen Wang of Portland OR (US) for intel corporation, Brent Carlton of Portland OR (US) for intel corporation
IPC Code(s): G06F9/50, G11C7/10
Abstract: systems, apparatuses and methods include technology that executes, with a compute-in-memory (cim) element, first computations based on first data associated with a workload, and a storage of the first data, executes, with a compute-near memory (cnm) element, second computations based on second data associated with the workload and executes, with a compute-outside-of-memory (com) element, third computations based on third data associated with the workload. the technology further receives, with a multiplexer, processed data from a first element of the cim element, the cnm element and the com element, and provides, with the multiplexer, the processed data to a second element of the cim element, the cnm element and the com element.
Inventor(s): Prashant CHAUDHARI of Folsom CA (US) for intel corporation, Jain PHILIP of Bangalore (IN) for intel corporation, James VALERIO of North Plains OR (US) for intel corporation, Murali RAMADOSS of Folsom CA (US) for intel corporation, Ankur SHAH of Folsom CA (US) for intel corporation, Jeffery S. BOLES of Folsom CA (US) for intel corporation, Aditya NAVALE of Folsom CA (US) for intel corporation
IPC Code(s): G06F9/50, G06F9/455
Abstract: apparatus and method for concurrent performance monitoring. for example, one embodiment of an apparatus comprises: compute hardware logic to concurrently process a number of workloads, the compute hardware logic to be subdivided into a plurality of compute hardware contexts based on the number of workloads; and programmable performance monitoring circuitry to be dynamically partitioned to perform parallel performance monitoring operations to monitor performance of each of the plurality of compute hardware contexts while the number of workloads are concurrently processed, the programmable performance monitoring circuitry to differentiate between performance monitoring data of different compute hardware contexts based on a unique identifier associated with each of the compute hardware contexts.
Inventor(s): Francesc Guim Bernat of Barcelona (ES) for intel corporation, Daniel Rivas Barragan of Cologne (DE) for intel corporation, Kshitij A. Doshi of Tempe AZ (US) for intel corporation, Mark A. Schmisseur of Phoenix AZ (US) for intel corporation
IPC Code(s): G06F13/16, G06F12/0817, H04L12/46, C07F15/00, G06F12/0831, G06F12/1018, H04L49/90
Abstract: in an example, there is disclosed a host-fabric interface (hfi), including: an interconnect interface to communicatively couple the hfi to an interconnect; a network interface to communicatively couple the hfi to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the hfi and a core communicatively coupled to the hfi via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.
20240045829.MULTI-DIMENSIONAL NETWORK SORTED ARRAY MERGING_simplified_abstract_(intel corporation)
Inventor(s): Robert Pawlowski of Beaverton OR (US) for intel corporation, Sriram Aananthakrishnan of Lubbock TX (US) for intel corporation
IPC Code(s): G06F15/173
Abstract: techniques for multi-dimensional network sorted array merging. a first switch of a plurality of switches of an apparatus may receive a first element of a first array and a first element of a second array. the first switch may determine that the first element of the first array is less than the first element of the second array. the first switch may cause the first element of the first array to be stored as a first element of an output array.
20240045830.SCALAR CORE INTEGRATION_simplified_abstract_(intel corporation)
Inventor(s): Joydeep RAY of Folsom CA (US) for intel corporation, Aravindh ANANTARAMAN of Folsom CA (US) for intel corporation, Abhishek R. APPU of El Dorado Hills CA (US) for intel corporation, Altug KOKER of El Dorado Hills CA (US) for intel corporation, Elmoustapha OULD-AHMED-VALL of Chandler AZ (US) for intel corporation, Valentin ANDREI of San Jose CA (US) for intel corporation, Subramaniam MAIYURAN of Gold River CA (US) for intel corporation, Nicolas GALOPPO VON BORRIES of Portland OR (US) for intel corporation, Varghese GEORGE of Folsom CA (US) for intel corporation, Mike MACPHERSON of Portland OR (US) for intel corporation, Ben ASHBAUGH of Folsom CA (US) for intel corporation, Murali RAMADOSS of Folsom CA (US) for intel corporation, Vikranth VEMULAPALLI of Folsom CA (US) for intel corporation, William SADLER of Folsom CA (US) for intel corporation, Jonathan PEARCE of Portland OR (US) for intel corporation, Sungye KIM of Folsom CA (US) for intel corporation
IPC Code(s): G06F15/80, G06F9/30, G06F9/38, G06T15/00
Abstract: methods and apparatus relating to scalar core integration in a graphics processor. in an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. other embodiments are also disclosed and claimed.
20240045968.COMPOSABLE TRUSTED EXECUTION ENVIRONMENTS_simplified_abstract_(intel corporation)
Inventor(s): Kapil Sood of Portland OR (US) for intel corporation, Ioannis T. Schoinas of Portland OR (US) for intel corporation, Yu-Yuan Chen of Chandler AZ (US) for intel corporation, Raghunandan Makaram of Northborough MA (US) for intel corporation, David J. Harriman of Portland OR (US) for intel corporation, Baiju Patel of Portland OR (US) for intel corporation, Ronald Perez of Piedmont CA (US) for intel corporation, Matthew E. Hoekstra of Forest Grove OR (US) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation
IPC Code(s): G06F21/57, G06F9/50, G06F21/85, G06F21/72, G06F21/53
Abstract: in one embodiment, an apparatus comprises a processor to: receive a request to configure a secure execution environment for a first workload; configure a first set of secure execution enclaves for execution of the first workload, wherein the first set of secure execution enclaves is configured on a first set of processing resources, wherein the first set of processing resources comprises one or more central processing units and one or more accelerators; configure a first set of secure datapaths for communication among the first set of secure execution enclaves during execution of the first workload, wherein the first set of secure datapaths is configured over a first set of interconnect resources; configure the secure execution environment for the first workload, wherein the secure execution environment comprises the first set of secure execution enclaves and the first set of secure datapaths.
Inventor(s): Michael DOYLE of San Jose CA (US) for intel corporation, Travis SCHLUESSLER of Berthoud CO (US) for intel corporation, Gabor LIKTOR of San Francisco CA (US) for intel corporation, Atsuo KUWAHARA of Novi MI (US) for intel corporation, Jefferson AMSTUTZ of Austin TX (US) for intel corporation
IPC Code(s): G06T1/20, G06F16/901, G06F9/38, G06F9/50, G06T15/00
Abstract: an apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.
Inventor(s): Noam Elron of Tel Aviv (IL) for intel corporation
IPC Code(s): G06T5/00
Abstract: an unsupervised technique for training a deep learning based temporal noise reducer on unlabeled real-world data. the unsupervised technique can also be used to calibrate the free parameters of a tnr based on algorithmic principles. the training is based on actual real-world video (which may include noise), and not based on video containing artificial or added noise. using the unsupervised technique to train a tnr allows the tnr to be tailored to the noise statistics of the use-case, resulting in the provision of high quality video with minimal resources.
Inventor(s): Noam Elron of Tel Aviv (IL) for intel corporation
IPC Code(s): G06T5/00
Abstract: the tnr can be based on an uncalibrated tnr's output in time-reverse, as well as the uncalibrated tnr's output in time-forward. the frames used for both the time-forward output and the time-reversed output can be frames from the past. the tnr is calibrated to minimize the difference between its time-forward output and its time-reversed output.
Inventor(s): Kyle ANDERSON of Austin TX (US) for intel corporation, Wesley J. HOLLAND of Austin TX (US) for intel corporation
IPC Code(s): G06T15/00, G06F3/01, G09G3/00, G06T1/60, G09G5/36, G09G5/00
Abstract: an apparatus and method for efficient image reprojection in a virtual reality system. for example, one embodiment of an apparatus comprises: a sensor interface to collect motion data from one or more sensors during a virtual reality session; graphics circuitry to execute graphics program code to render an image frame during the virtual reality session; a processor to generate motion transform data using the motion data, the motion transform data specifying how the image frame is to be adjusted prior to display; a reprojection engine to perform an in-line reprojection of the frame using the motion transform data to generate a reprojected image frame; and display circuitry to display the reprojected frame.
Inventor(s): Ingo WALD of Salt Lake City UT (US) for intel corporation, Carsten BENTHIN of Voelklingen (DE) for intel corporation, Sven WOOP of Volklingen (DE) for intel corporation
IPC Code(s): G06T15/06, G06T7/50, G06T15/00, G06T15/50
Abstract: apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. for example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. the shader execution circuitry includes a plurality of single instruction multiple data (simd) execution units. sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for simd operations performed by the simd execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (bvhs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
Inventor(s): Liuyang Yang of Portland OR (US) for intel corporation, Yair Yona of Cupertino CA (US) for intel corporation, Moreno Ambrosin of Hillsboro OR (US) for intel corporation, Xiruo Liu of Portland CA (US) for intel corporation, Hosein Nikopour of San Jose CA (US) for intel corporation, Shilpa Talwar of Cupertino CA (US) for intel corporation, Kathiravetpillai Sivanesan of Portland OR (US) for intel corporation, Sridhar Sharma of Palo Alto CA (US) for intel corporation, Debabani Choudhury of Thousand Oaks CA (US) for intel corporation, Kuilin Clark Chen of Hillsboro OR (US) for intel corporation, Jeffrey Ota of Morgan Hill CA (US) for intel corporation, Justin Gottschlich of Santa Clara CA (US) for intel corporation
IPC Code(s): G08G1/00, G01S5/14, H04W4/40, G08G1/052, G01S5/02
Abstract: methods, apparatus, systems and articles of manufacture are disclosed to validate data communicated by a vehicle. an example apparatus an anomaly detector to, in response to data communicated by a vehicle, at least one of compare an estimated speed with a reported speed or compare a location of the vehicle with a reported location. the apparatus including the anomaly detector further to generate an indication of the vehicle in response to the comparison. the apparatus further includes a notifier to discard data sent by the vehicle and notify surrounding vehicles of the data communicated by the vehicle.
Inventor(s): Rami HOURANI of Beaverton OR (US) for intel corporation, Richard VREELAND of Beaverton OR (US) for intel corporation, Giselle ELBAZ of Portland OR (US) for intel corporation, Manish CHANDHOK of Beaverton OR (US) for intel corporation, Richard E. SCHENKER of Portland OR (US) for intel corporation, Gurpreet SINGH of Portland OR (US) for intel corporation, Florian GSTREIN of Portland OR (US) for intel corporation, Nafees KABIR of Portland OR (US) for intel corporation, Tristan A. TRONIC of Aloha OR (US) for intel corporation, Eungnak HAN of Portland OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L29/78, H01L23/522, H01L29/417, H01L27/088, H01L21/8234
Abstract: contact over active gate structures with metal oxide cap structures are described. in an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. a plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. an interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. an opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. a conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.
Inventor(s): Andrew W. YEOH of Portland OR (US) for intel corporation, Joseph STEIGERWALD of Forest Grove OR (US) for intel corporation, Jinhong SHIN of Portland OR (US) for intel corporation, Vinay CHIKARMANE of Portland OR (US) for intel corporation, Christopher P. AUTH of Portland OR (US) for intel corporation
IPC Code(s): H01L29/66, H10B10/00, H01L21/02, H01L21/033, H01L21/28, H01L21/285, H01L21/308, H01L21/311, H01L21/762, H01L21/768, H01L21/8234, H01L21/8238, H01L23/522, H01L23/528, H01L23/532, H01L27/02, H01L27/088, H01L27/092, H01L29/06, H01L29/08, H01L29/165, H01L29/167, H01L29/417, H01L29/51, H01L29/78
Abstract: embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ild layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. a second plurality of conductive interconnect lines is in and spaced apart by a second ild layer above the first ild layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.
Inventor(s): Willy RACHMADY of Beaverton OR (US) for intel corporation, Gilbert DEWEY of Beaverton OR (US) for intel corporation, Jack T. KAVALIEROS of Portland OR (US) for intel corporation, Aaron LILAK of Beaverton OR (US) for intel corporation, Patrick MORROW of Portland OR (US) for intel corporation, Anh PHAN of Beaverton OR (US) for intel corporation, Cheng-Ying HUANG of Hillsboro OR (US) for intel corporation, Ehren MANNEBACH of Beaverton OR (US) for intel corporation
IPC Code(s): H01L29/66, H01L21/02, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/786
Abstract: gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. for example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. the vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. a gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.
Inventor(s): Rishabh MEHANDRU of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Stephen CEA of Hillsboro OR (US) for intel corporation, Biswajeet GUHA of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/775, H01L29/417, H01L29/423, H01L29/66, H01L29/786
Abstract: wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. in an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. a gate structure surrounds a channel portion of the semiconductor nanowire. a source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. a conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.
Inventor(s): Ramesh Vankunavath of Bangalore (IN) for intel corporation, Shailendra Singh Chauhan of Bengaluru (IN) for intel corporation, N.V.S Kumar Srighakollapu of Bengaluru (IN) for intel corporation, Ankur Mishra of Bangalore (IN) for intel corporation
IPC Code(s): H02J7/00
Abstract: techniques and mechanisms for improving an efficiency of power delivery resources. in one embodiment, switch circuitry is operated based on an indication from an integrated circuit (ic) die that circuitry of the ic die is ready to accommodate a low power state which disables a delivery of power to the ic die by a voltage regulator (vr). the switch circuitry is operated, based on a control signal is also used to disable said power delivery, to disable or otherwise prevent one or more conductive paths which are each between a respective two of a battery pack, a voltage regulator, or a battery charger. in another embodiment, the low power state enable a rail for circuitry which is to provide a real time clock signal to the ic die, but disables any other rails which power the ic die.
Inventor(s): Ashoke RAVI of Portland OR (US) for intel corporation, Ronen KRONFELD of Shoham (IL) for intel corporation, Ofir DEGANI of Haifa (IL) for intel corporation
IPC Code(s): H04L7/033
Abstract: a radio-frequency integrated circuit (rfic) configured to generate a synthesized clock includes a phase locked loop (pll) configured to divide down a clock to a non-harmonic frequency; a plurality of multi-phase injection locked clock multipliers (ilcm) directly connected to a plurality of transceiver chains; wherein the pll is further configured to distribute a divided down clock to at least one of the plurality of multi-phase ilcms; wherein the plurality of multiphase ilcms are configured to select a phase of and multiply the divided down clock to synthesize a desired harmonic frequency of the clock and suppress an undesired harmonic frequency of the clock.
Inventor(s): Ping Yu of Shanghai (CN) for intel corporation, Tomasz Kantecki of Ennis (IE) for intel corporation, Chao Dou of Shanghai (CN) for intel corporation, Pablo De Lara Guarch of Shannon CE (IE) for intel corporation, Brian Will of Phoenix AZ (US) for intel corporation
IPC Code(s): H04L9/40, H04L69/22
Abstract: an apparatus includes an interface to memory, and a processor to execute one or more instructions. the instructions cause the processor to receive, via an application programming interface (api), a plurality of packets, respective packets of the plurality of packets comprising a respective header and a respective payload. further, the instructions cause the processor to determine, by a quic protocol stack, to encrypt the plurality of packets in parallel. further, the instructions cause the processor to encrypt the payloads of the plurality of packets in parallel. further, the instructions cause the processor to encrypt the headers of the plurality of packets in parallel.
Inventor(s): Silviu Petria of Stilpeni (RO) for intel corporation, George Milescu of Bucharest (RO) for intel corporation, Bogdan Davidoaia of Giurgiu (RO) for intel corporation
IPC Code(s): H04L65/61, H04L69/14, H04L65/612, H04L65/75, H04L67/56, H04W40/02, H04W76/30
Abstract: examples of systems and methods for network proxy server for energy efficient video streaming on mobile devices are generally described herein. a proxy server to deliver video content may include a communication module to intercept a request for video content from a mobile device, the request for video content intended for a content server and forward a modified request for the video content to the content server. the communication module may receive the video content from the content server and transfer a portion of the video content to the mobile device using a multipath transport protocol.
Inventor(s): Jerin C. Justin of San Jose CA (US) for intel corporation, Kumar Balasubramanian of Chandler AZ (US) for intel corporation
IPC Code(s): H04L67/125, G06F11/30, G06F11/34, H04L67/01, G06F30/20, G06F11/26, H04L67/025
Abstract: a system and method for representing events that occur in a real world deployment is described. a real-world workload including multiple events is identified. multiple characteristics of the real-world workload are converted into multiple endpoint simulator workloads. multiple gateway hardware characteristics are converted into a modeling elements for simulated internet of things (iot) networks. further, a simulation is performed for each of the endpoint simulator workloads on each of the simulated iot networks. also, statistics are collected about the performance of the simulated iot networks for the endpoint simulator workloads.
Inventor(s): Jason Tanner of Folsom CA (US) for intel corporation, Stanley Baran of Chandler AZ (US) for intel corporation, Kristoffer Fleming of Chandler AZ (US) for intel corporation, Chia-Hung S. Kuo of Folsom CA (US) for intel corporation, Sankar Radhakrishnan of Bothell WA (US) for intel corporation, Venkateshan Udhayan of Portland OR (US) for intel corporation
IPC Code(s): H04N19/162, H04N19/105, H04N19/172, H04N19/46
Abstract: a computer-implemented method of video coding comprises receiving at least one frame of a video sequence of an interactive application interface associated with at least one asset displayable on the interface in response to a user action related to the interface. the method includes encoding the at least one frame. the method also includes transmitting the at least one asset and the encoded at least one frame to a remote device. the transmitting operation refers to performing the transmitting regardless of whether a request to display the at least one asset exists. the asset can be a non-persistent asset on the frame only while a user performs a continuous action or maintains a cursor at a specific place on the interface. the asset also can be a persistent asset on the frame in response to a first action and is removed from the display in response to a second action.
Inventor(s): Qinghua LI of San Ramon CA (US) for intel corporation, Juan Fang of Portland OR (US) for intel corporation, Po-Kai Huang of San Jose CA (US) for intel corporation, Robert Stacey of Portland OR (US) for intel corporation, Laurent Cariou of Milizac (FR) for intel corporation
IPC Code(s): H04W40/22, H04L45/74
Abstract: provided herein are apparatuses and methods for multiplexed transmission and reception of relay node. an apparatus includes interface circuitry; and processor circuitry coupled with the interface circuitry, wherein the processor circuitry is to: decode a first-hop message received from a first node via the interface circuitry to obtain a message body; generate, in response to the first-hop message, a first-hop response message for transmission to the first node; generate a second-hop message including the message body for transmission to a second node; and multiplex the first-hop response message with the second-hop message in a same frame for transmission of the first-hop response message and the second-hop message simultaneously. other embodiments are described and claimed.
Inventor(s): Yingyang Li of Beijing (CN) for intel corporation, Gang Xiong of Beaverton OR (US) for intel corporation, Bishwarup Mondal of San Ramon CA (US) for intel corporation, Dae Won Lee of Portland OR (US) for intel corporation
IPC Code(s): H04W72/1273, H04W72/044, H04W48/10, H04W72/30
Abstract: a generation-node b (gnb) configured for unlicensed spectrum operation above 52.6 ghz in a fifth-generation new-radio (nr) system (5gs) may encode a parameter (e.g., ssb-positionsinburst) for transmission to a ue (e.g., in the sib1 or ue specific rrc signalling). the parameter may indicate candidate positions of synchronization signal blocks (ssbs) within a discovery reference signal (drs) measurement timing configuration (dmtc) transmission window within slots of a system frame (sfn). during the dmtc window, the gnb may perform a lbt procedure on an unlicensed carrier of the unlicensed spectrum to determine if the unlicensed carrier is available. when the lbt is successful (i.e., the unlicensed carrier is available), the gnb may encode a discovery reference signal (drs) for transmission on the unlicensed carrier. the drs may include one or more of the ssbs transmitted during the candidate positions that fall within the drs. the gnb may perform rate matching around the ssbs for a scheduled pdsch based on the indicated parameter and transmit the rate-matched pdsch.
Inventor(s): Oner ORHAN of San Jose CA (US) for intel corporation, Hosein NIKOPOUR of San Jose CA (US) for intel corporation
IPC Code(s): H04W72/12, G06N3/04
Abstract: a device may include a processor configured to provide input data that is based on channel information representative of attributes associated with one or more established communication channels of a plurality of communication devices to a trained machine learning model configured to determine a score for each of the plurality of communication devices based on the input data, wherein the score represents a likelihood of the respective communication device to be scheduled for a communication resource to perform a communication, determine, for the communication resource, one or more communication devices from the plurality of communication devices based on the determined score for each of the plurality of communication devices, and provide an output to schedule the communication resource for the one or more communication devices
Inventor(s): Ofer Hareuveni of Haifa (IL) for intel corporation, Daniel Cohn of Raanana (IL) for intel corporation, David Birnbaum of Modiin (IL) for intel corporation, Ehud Reshef of Qiryat Tivon (IL) for intel corporation, Dor Chay of Haifa (IL) for intel corporation, Sivan Koffler of Raanana (IL) for intel corporation
IPC Code(s): H04W76/15, H04W80/02, H04W12/06, H04L61/5014
Abstract: for example, a wireless communication device may be configured to, while communicating via a first radio of the wireless communication device over a first network connection in a first wlan over a first wireless communication frequency band, identify a second wlan over a second wireless communication frequency band for concurrent multiple band (cmb) network access, the second wireless communication frequency band different from the first wireless communication frequency band; based on identifying the second wlan, to automatically transmit from a second radio of the wireless communication device user credentials to establish a second network connection with the second wlan over the second wireless communication frequency band, the second network connection concurrent with the first network connection; and to concurrently communicate over the first and second network connections by routing to the first and second radios a plurality of application streams corresponding to one or more applications.
20240049450.CAPACITOR CONNECTIONS IN DIELECTRIC LAYERS_simplified_abstract_(intel corporation)
Inventor(s): Travis W. LAJOIE of Forest Grove OR (US) for intel corporation, Abhishek A. SHARMA of Hillsboro OR (US) for intel corporation, Van H. LE of Portland OR (US) for intel corporation, Chieh-Jen KU of Hillsboro OR (US) for intel corporation, Pei-Hua WANG of Beaverton OR (US) for intel corporation, Jack T. KAVALIEROS of Portland OR (US) for intel corporation, Bernhard SELL of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Gregory GEORGE of Beaverton OR (US) for intel corporation, Akash GARG of Portland OR (US) for intel corporation, Allen B. GARDINER of Portland OR (US) for intel corporation, Shem OGADHOH of Beaverton OR (US) for intel corporation, Juan G. ALZATE VINASCO of Tigard OR (US) for intel corporation, Umut ARSLAN of Portland OR (US) for intel corporation, Fatih HAMZAOGLU of Portland OR (US) for intel corporation, Nikhil MEHTA of Portland OR (US) for intel corporation, Jared STOEGER of Portland OR (US) for intel corporation, Yu-Wen HUANG of Beaverton OR (US) for intel corporation, Shu ZHOU of Portland OR (US) for intel corporation
IPC Code(s): H10B12/00, H01L27/12
Abstract: embodiments herein describe techniques for a semiconductor device including a substrate. a first capacitor includes a first top plate and a first bottom plate above the substrate. the first top plate is coupled to a first metal electrode within an inter-level dielectric (ild) layer to access the first capacitor. a second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ild layer to access the second capacitor. the second metal electrode is disjoint from the first metal electrode. the first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. other embodiments may be described and/or claimed.
- INTEL CORPORATION
- G06F1/329
- G06F1/3228
- G06F9/38
- G06F9/48
- Intel corporation
- G06F7/483
- G06F9/30
- G06F7/487
- G06F17/16
- G06F9/455
- H04L9/06
- G06F9/50
- G11C7/10
- G06F13/16
- G06F12/0817
- H04L12/46
- C07F15/00
- G06F12/0831
- G06F12/1018
- H04L49/90
- G06F15/173
- G06F15/80
- G06T15/00
- G06F21/57
- G06F21/85
- G06F21/72
- G06F21/53
- G06T1/20
- G06F16/901
- G06T5/00
- G06F3/01
- G09G3/00
- G06T1/60
- G09G5/36
- G09G5/00
- G06T15/06
- G06T7/50
- G06T15/50
- G08G1/00
- G01S5/14
- H04W4/40
- G08G1/052
- G01S5/02
- H01L29/423
- H01L29/78
- H01L23/522
- H01L29/417
- H01L27/088
- H01L21/8234
- H01L29/66
- H10B10/00
- H01L21/02
- H01L21/033
- H01L21/28
- H01L21/285
- H01L21/308
- H01L21/311
- H01L21/762
- H01L21/768
- H01L21/8238
- H01L23/528
- H01L23/532
- H01L27/02
- H01L27/092
- H01L29/06
- H01L29/08
- H01L29/165
- H01L29/167
- H01L29/51
- H01L29/786
- H01L29/775
- H02J7/00
- H04L7/033
- H04L9/40
- H04L69/22
- H04L65/61
- H04L69/14
- H04L65/612
- H04L65/75
- H04L67/56
- H04W40/02
- H04W76/30
- H04L67/125
- G06F11/30
- G06F11/34
- H04L67/01
- G06F30/20
- G06F11/26
- H04L67/025
- H04N19/162
- H04N19/105
- H04N19/172
- H04N19/46
- H04W40/22
- H04L45/74
- H04W72/1273
- H04W72/044
- H04W48/10
- H04W72/30
- H04W72/12
- G06N3/04
- H04W76/15
- H04W80/02
- H04W12/06
- H04L61/5014
- H10B12/00
- H01L27/12
- G06F9/30145
- G06F9/3001
