Apple inc. (20240106440). SYSTEMS AND METHODS FOR PROVIDING A DELAY-LOCKED LOOP WITH COARSE TUNING TECHNIQUE simplified abstract

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SYSTEMS AND METHODS FOR PROVIDING A DELAY-LOCKED LOOP WITH COARSE TUNING TECHNIQUE

Organization Name

apple inc.

Inventor(s)

Chen Zhai of San Diego CA (US)

Abbas Komijani of Mountain View CA (US)

SYSTEMS AND METHODS FOR PROVIDING A DELAY-LOCKED LOOP WITH COARSE TUNING TECHNIQUE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240106440 titled 'SYSTEMS AND METHODS FOR PROVIDING A DELAY-LOCKED LOOP WITH COARSE TUNING TECHNIQUE

Simplified Explanation

In order to increase the operating frequency range of a delay-locked loop (DLL) while decreasing varactor sizes, coarse tuning circuitry may be implemented in the DLL. The DLL includes a voltage-controlled delay line (VCDL) with multiple switched capacitors coupled in parallel to each other. The coarse tuning circuitry is electrically coupled to a phase detector and the multiple switched capacitors of the VCDL, allowing it to adjust switched capacitor loading based on the signal received from the phase detector.

  • Voltage-controlled delay line (VCDL) with multiple switched capacitors in parallel
  • Coarse tuning circuitry adjusts switched capacitor loading based on phase detector signal
  • Increases DLL tuning range and decreases phase noise

Potential Applications

The technology can be applied in high-frequency communication systems, radar systems, and frequency synthesizers.

Problems Solved

This innovation solves the problem of limited operating frequency range in DLLs and the need for smaller varactor sizes.

Benefits

The technology increases DLL tuning range, decreases phase noise, and allows for more precise frequency control.

Potential Commercial Applications

Potential commercial applications include telecommunications equipment, test and measurement devices, and aerospace systems.

Possible Prior Art

Prior art may include patents related to delay-locked loops, voltage-controlled delay lines, and frequency tuning circuits.

Unanswered Questions

How does the coarse tuning circuitry impact the overall power consumption of the DLL?

The article does not provide information on how the implementation of coarse tuning circuitry affects the power consumption of the DLL.

Are there any limitations to the frequency range extension achieved by this technology?

The article does not address any potential limitations or constraints on the frequency range extension capabilities of the DLL with coarse tuning circuitry.


Original Abstract Submitted

to increase the operating frequency range of the dll while decreasing varactor sizes, coarse tuning circuitry may be implemented in a delay-locked loop (dll). the dll may include a voltage-controlled delay line (vcdl) including multiple switched capacitors coupled in parallel to each other. an electrical ground may be coupled to the parallel switched capacitors at a first node and a buffer and variable capacitor may be coupled to the parallel switched capacitors at a second node. the coarse tuning circuitry may be electrically coupled to a phase detector and to the multiple switched capacitors of the vcdl, such that the coarse tuning circuitry may receive a signal (e.g., an indication of a phase) from the phase detector and may adjust switched capacitor loading based on the signal received from the phase detector. such a dll implementation may increase dll tuning range and decrease phase noise, among other advantages.