Advanced micro devices, inc. (20240112747). SIGNAL INTERFERENCE TESTING USING RELIABLE READ WRITE INTERFACE simplified abstract
Contents
- 1 SIGNAL INTERFERENCE TESTING USING RELIABLE READ WRITE INTERFACE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SIGNAL INTERFERENCE TESTING USING RELIABLE READ WRITE INTERFACE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SIGNAL INTERFERENCE TESTING USING RELIABLE READ WRITE INTERFACE
Organization Name
Inventor(s)
Tahsin Askar of Round Rock TX (US)
Naveen Davanam of Austin TX (US)
Kedarnath Balakrishnan of Bangalore (IN)
Kevin M. Brandl of Austin TX (US)
James R. Magro of Lakeway TX (US)
SIGNAL INTERFERENCE TESTING USING RELIABLE READ WRITE INTERFACE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240112747 titled 'SIGNAL INTERFERENCE TESTING USING RELIABLE READ WRITE INTERFACE
Simplified Explanation
The memory controller described in the abstract includes a test circuit that generates testing sequences of read and write commands for each channel, transmitting them simultaneously without being selected by the arbiters.
- Memory controller with first and second arbiters for selecting memory commands for dispatch over different channels
- Test circuit generates testing sequences of read and write commands for each channel
- Testing sequences are transmitted simultaneously over channels without arbiter selection
Potential Applications
The technology could be applied in:
- High-speed memory systems
- Data centers
- Embedded systems
Problems Solved
The memory controller helps in:
- Efficient testing of memory channels
- Simultaneous transmission of testing sequences
- Avoiding delays in memory testing
Benefits
The benefits of this technology include:
- Improved memory testing efficiency
- Faster identification of memory issues
- Enhanced reliability of memory systems
Potential Commercial Applications
This technology could be used in:
- Memory module manufacturing
- Computer hardware testing
- Server maintenance and diagnostics
Possible Prior Art
One possible prior art could be the use of separate testing circuits for each memory channel, which may not allow for simultaneous testing sequences.
Unanswered Questions
1. How does the test circuit ensure that the testing sequences do not interfere with each other during simultaneous transmission? 2. Are there any limitations to the number of testing sequences that can be generated and transmitted simultaneously by the test circuit?
Original Abstract Submitted
a memory controller includes a first arbiter for selecting memory commands for dispatch to a memory over a first channel, a second arbiter for selecting memory commands for dispatch to the memory over a second channel, and a test circuit. the test circuit generates a respective testing sequence of read commands and write commands for each of the first channel and second channel, and causes the testing sequences to be transmitted over the first and second channels at least partially overlapping in time without selection by the first or second arbiters.
