20240086345.MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE simplified abstract (samsung electronics co., ltd.)
Contents
- 1 MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE
Organization Name
Inventor(s)
Nam Sung Kim of Yongin-si (KR)
MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240086345 titled 'MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE
Simplified Explanation
The memory device described in the abstract includes a buffer die and a plurality of core dies stacked on top of the buffer die. The core dies consist of processing circuits, memory cell arrays, command decoders, and data input/output circuits. The buffer die receives broadcast commands from an external device, which are then decoded and executed by the core dies to transfer data through a common data input/output bus.
- Buffer die receives broadcast commands from an external device.
- Core dies stacked on the buffer die consist of processing circuits, memory cell arrays, command decoders, and data input/output circuits.
- Command decoders decode broadcast commands and control data transfer through a common data input/output bus.
Potential Applications
The technology described in this patent application could be applied in:
- High-performance computing systems
- Data centers
- Networking equipment
Problems Solved
This technology helps in:
- Improving data transfer efficiency
- Enhancing memory access speed
- Streamlining communication between different processing units
Benefits
The benefits of this technology include:
- Increased overall system performance
- Reduced latency in data transfer
- Enhanced scalability for future memory requirements
Potential Commercial Applications
The potential commercial applications of this technology could be in:
- Server systems
- Supercomputers
- Artificial intelligence applications
Possible Prior Art
One possible prior art for this technology could be:
- Stacked memory devices with integrated processing units
Unanswered Questions
How does this technology impact power consumption in memory devices?
The article does not provide information on the power consumption implications of this technology.
What are the potential limitations of stacking multiple core dies on a buffer die?
The article does not address any potential limitations or challenges that may arise from this stacking configuration.
Original Abstract Submitted
a memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. the plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.
