20240057310. SEMICONDUCTOR MEMORY DEVICE simplified abstract (Fujian Jinhua Integrated Circuit Co., Ltd.)

SEMICONDUCTOR MEMORY DEVICE

Organization Name

Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor(s)

Yincong Hong of Quanzhou City (CN)

Chia-Hung Wang of Quanzhou City (CN)

Yue Liu of Quanzhou City (CN)

Chung-Ping Hsia of Quanzhou City (CN)

SEMICONDUCTOR MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240057310 titled 'SEMICONDUCTOR MEMORY DEVICE

Simplified Explanation

The semiconductor memory device described in the patent application includes a substrate, contact pads, and a capacitor array structure on an array region of the substrate. The capacitor array structure consists of capacitors on the contact pads and a middle supporting layer between waist portions of the capacitors.

• The capacitor array structure includes capacitors on contact pads and a middle supporting layer.
• The capacitors have upper and lower portions defined by the middle supporting layer.
• The lower portions of the capacitors near the edge of the array region are tilted.
• The upper portions of the capacitors near the edge of the array region have misalignments to the contact pads.
• The design aims to reduce stress in the capacitor array structure of the semiconductor memory device.

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1. 1. 1. Potential Applications

• Semiconductor memory devices
• Integrated circuits
• Electronic devices requiring memory storage

1. 1. 1. Problems Solved

• Reducing stress in the capacitor array structure
• Improving alignment of capacitors to contact pads
• Enhancing reliability and performance of semiconductor memory devices

1. 1. 1. Benefits

• Increased durability and longevity of semiconductor memory devices
• Improved functionality and efficiency of integrated circuits
• Enhanced overall performance of electronic devices

Original Abstract Submitted

a semiconductor memory device includes a substrate, and a plurality of contact pads and a capacitor array structure disposed on an array region of the substrate. the capacitor array structure includes a plurality of capacitors respectively disposed on the contact pads and a middle supporting layer extending laterally between waist portions of the capacitors to define an upper portion and a lower portion of each of the capacitors. the lower portions of the capacitors near the edge of the array region are tilted. the upper portions of the capacitors near the edge of the array region have misalignments to the contact pads. the stress in the capacitor array structure of the semiconductor memory device may be reduced.