20240054098. FETCHING VECTOR DATA ELEMENTS WITH PADDING simplified abstract (TEXAS INSTRUMENTS INCORPORATED)
Contents
FETCHING VECTOR DATA ELEMENTS WITH PADDING
Organization Name
TEXAS INSTRUMENTS INCORPORATED
Inventor(s)
Joseph Zbiciak of San Jose CA (US)
FETCHING VECTOR DATA ELEMENTS WITH PADDING - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240054098 titled 'FETCHING VECTOR DATA ELEMENTS WITH PADDING
Simplified Explanation
The abstract describes a streaming engine used in a digital data processor that generates a fixed read-only data stream with nested loops. An address generator produces addresses for data elements in the loops, while a stream head register stores data elements to be used as operands by functional units. A stream template register specifies a circular address mode for the loops, along with block size numbers and block size selection.
- The streaming engine specifies a fixed read-only data stream with nested loops.
- An address generator produces addresses for data elements in the loops.
- A stream head register stores data elements for use as operands by functional units.
- A stream template register specifies a circular address mode, block size numbers, and block size selection.
- Potential Applications
- This technology could be used in digital signal processing applications. - It could be applied in multimedia processing for efficient data streaming.
- Problems Solved
- Efficiently generating and accessing data streams with nested loops. - Simplifying the process of specifying circular address modes and block sizes.
- Benefits
- Improved performance in data processing tasks. - Simplified design and implementation of streaming engines in digital data processors.
Original Abstract Submitted
a streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. an address generator produces address of data elements for the nested loops. a steam head register stores data elements next to be supplied to functional units for use as operands. a stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. for a first circular address block size selection the block size corresponds to the first block size number. for a first circular address block size selection the block size corresponds to the first block size number. for a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.
