20240038872. GATE PROFILE TUNING FOR MULTIGATE DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

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GATE PROFILE TUNING FOR MULTIGATE DEVICE

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Cheng-I Lin of Hsinchu (TW)

Hao-Ming Tang of Taipei City (TW)

Shu-Han Chen of Hsinchu City (TW)

Chi On Chui of Hsinchu City (TW)

GATE PROFILE TUNING FOR MULTIGATE DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240038872 titled 'GATE PROFILE TUNING FOR MULTIGATE DEVICE

Simplified Explanation

The patent application describes a method for tuning the gate profile in a gate structure used in electronic devices. The method involves forming a gate structure with a dummy gate and gate spacers on the sidewalls of the dummy gate. The dummy gate is partially removed to create a gate opening that defines the gate profile. The gate profile is then modified by treating portions of the gate spacers, such as with oxygen plasma treatment, and removing the treated portions of the gate spacers, such as by oxide removal. After removing the remainder of the dummy gate, a gate stack is formed in the gate opening, which has a funnel-shaped profile.

  • The method involves forming a gate structure with a dummy gate and gate spacers.
  • The gate profile is modified by treating and removing portions of the gate spacers.
  • A gate stack with a funnel-shaped profile is formed in the gate opening.
  • The width of the gate stack above the channel layer is greater than the width below the channel layer.

Potential applications of this technology:

  • This gate profile tuning method can be applied in the fabrication of various electronic devices, such as transistors and integrated circuits.
  • It can improve the performance and efficiency of these electronic devices by optimizing the gate profile.

Problems solved by this technology:

  • Traditional gate structures may have suboptimal gate profiles, leading to reduced device performance.
  • This method allows for precise tuning of the gate profile, addressing this issue and improving device performance.

Benefits of this technology:

  • The gate profile tuning method enables the creation of gate structures with optimized profiles, resulting in improved device performance.
  • It provides a more efficient and effective way to tune the gate profile compared to traditional methods.
  • The method can be easily integrated into existing fabrication processes, minimizing the need for significant changes or additional equipment.


Original Abstract Submitted

gate profile tuning techniques are disclosed herein. an exemplary gate profile tuning method includes forming a gate structure over a channel layer. the gate structure includes a dummy gate and gate spacers disposed along sidewalls of the dummy gate. the method further includes partially removing the dummy gate to form a gate opening that defines a gate profile. the gate profile is then modified by treating portions of the gate spacers (for example, by oxygen plasma treatment) and removing the treated portions of the gate spacers (for example, by oxide removal). after removing a remainder of the dummy gate to expose the channel layer, a gate stack of the gate structure is formed in the gate opening. the gate stack has a funnel-shaped profile. in some embodiments, a width of the gate stack above the channel layer is greater than a width of the gate stack below the channel layer.