20240021578. WAFER-LEVEL HETEROGENEOUS DIES INTEGRATION STRUCTURE AND METHOD simplified abstract (ZHEJIANG LAB)
WAFER-LEVEL HETEROGENEOUS DIES INTEGRATION STRUCTURE AND METHOD
Organization Name
Inventor(s)
Jianliang Shen of Hangzhou (CN)
WAFER-LEVEL HETEROGENEOUS DIES INTEGRATION STRUCTURE AND METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240021578 titled 'WAFER-LEVEL HETEROGENEOUS DIES INTEGRATION STRUCTURE AND METHOD
Simplified Explanation
The abstract of the patent application describes a wafer-level heterogeneous dies integration structure and method. The structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to the upper surface of the wafer substrate, while the configuration substrate is connected to the lower surface of the wafer substrate. Through silicon vias on the lower surface of the wafer substrate connect it to the configuration substrate. The upper surface of the wafer substrate has re-distributed layers and a standardized micro bump array to form a standard integration zone connected to the standard integration module.
- Wafer-level heterogeneous dies integration structure and method
- Includes wafer substrate, silicon interposer, heterogeneous dies, and configuration substrate
- Heterogeneous dies connected to silicon interposer define a standard integration module
- Standard integration module connected to upper surface of wafer substrate
- Configuration substrate connected to lower surface of wafer substrate
- Through silicon vias on lower surface of wafer substrate connect it to configuration substrate
- Upper surface of wafer substrate has re-distributed layers and standardized micro bump array
- Forms standard integration zone connected to standard integration module
Potential Applications
- Semiconductor industry
- Electronics manufacturing
- Integrated circuit design and production
Problems Solved
- Integration of heterogeneous dies at the wafer level
- Efficient connection and communication between different dies
- Simplification of the integration process
Benefits
- Improved performance and functionality of integrated circuits
- Higher density and miniaturization of electronic devices
- Cost-effective manufacturing process
- Enhanced reliability and durability of integrated systems
Original Abstract Submitted
a wafer-level heterogeneous dies integration structure and method are provided. the integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. a standard integration module is defined by the heterogeneous dies connected to the silicon interposer. the standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. the wafer substrate is connected to the configuration substrate via through silicon vias on lower surface of the wafer substrate. and the upper surface of the wafer substrate is provided with re-distributed layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.
