20240012573. WRITE TRAINING IN MEMORY DEVICES simplified abstract (Lodestar Licensing Group, LLC)
Contents
WRITE TRAINING IN MEMORY DEVICES
Organization Name
Inventor(s)
Luigi Pilolli of L'Aquila (IT)
Ali Feiz Zarrin Ghalam of Sunnyvale CA (US)
Qiang Tang of Cupertino CA (US)
WRITE TRAINING IN MEMORY DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240012573 titled 'WRITE TRAINING IN MEMORY DEVICES
Simplified Explanation
The abstract describes a memory device that includes input/output (i/o) nodes, a circuit, a latch, a memory, and control logic. The i/o nodes receive a predefined data pattern, and the circuit adjusts a delay for each i/o node as the data pattern is received. The latch latches the data received on each i/o node, and the memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each i/o node based on the comparison.
- The memory device has multiple i/o nodes that receive a predefined data pattern.
- A circuit adjusts the delay for each i/o node as the data pattern is received.
- A latch captures and stores the data received on each i/o node.
- The memory stores the latched data.
- Control logic compares the stored latched data to an expected data pattern.
- The delay for each i/o node is set based on the comparison.
Potential applications of this technology:
- Memory testing and verification in computer systems.
- Data transmission and reception in communication systems.
- Signal processing and synchronization in electronic devices.
- Error detection and correction in data storage systems.
Problems solved by this technology:
- Ensures accurate and reliable data storage and retrieval.
- Facilitates efficient data transmission and reception.
- Helps identify and correct errors in data processing.
- Enables synchronization of multiple devices in a system.
Benefits of this technology:
- Improved data integrity and reliability.
- Enhanced system performance and efficiency.
- Reduced data processing errors and improved accuracy.
- Simplified testing and verification of memory systems.
Original Abstract Submitted
a memory device includes a plurality of input/output (i/o) nodes, a circuit, a latch, a memory, and control logic. the plurality of i/o nodes receive a predefined data pattern. the circuit adjusts a delay for each i/o node as the predefined data pattern is received. the latch latches the data received on each i/o node. the memory stores the latched data. the control logic compares the stored latched data to an expected data pattern and sets the delay for each i/o node based on the comparison.
