18541878. SEMICONDUCTOR PACKAGES WITH ANTENNAS simplified abstract (Intel Corporation)

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SEMICONDUCTOR PACKAGES WITH ANTENNAS

Organization Name

Intel Corporation

Inventor(s)

Telesphor Kamgaing of Chandler AZ (US)

Adel A. Elsherbini of Chandler AZ (US)

Sasha Oster of Chandler AZ (US)

SEMICONDUCTOR PACKAGES WITH ANTENNAS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18541878 titled 'SEMICONDUCTOR PACKAGES WITH ANTENNAS

Simplified Explanation

The patent application describes systems and methods for fabricating a coreless semiconductor package with an asymmetric build-up layer count, potentially reducing fabrication costs. The package may include dummification elements near antenna layers to improve antenna gain and efficiency.

  • The patent application focuses on the fabrication of a coreless semiconductor package with an asymmetric build-up layer count.
  • The package can be fabricated on both sides of a temporary substrate, potentially reducing overall layer count and fabrication costs.
  • Dummification elements near antenna layers can reduce image current, improving antenna gain and efficiency.

Potential Applications

The technology described in the patent application could be applied in the following areas:

  • Semiconductor packaging industry
  • Millimeter-wave antenna systems
  • Wireless communication devices

Problems Solved

The technology addresses the following issues:

  • High fabrication costs of semiconductor packages
  • Image current interference in antenna systems
  • Limited antenna gain and efficiency

Benefits

The technology offers the following benefits:

  • Cost reduction in semiconductor package fabrication
  • Improved antenna gain and efficiency
  • Enhanced performance of millimeter-wave antenna packages

Potential Commercial Applications

The technology has potential commercial applications in:

  • Semiconductor manufacturing companies
  • Telecommunications industry
  • Consumer electronics sector

Possible Prior Art

One possible prior art in this field is the use of dummy elements in semiconductor packaging to reduce interference and improve performance. Additionally, advancements in millimeter-wave antenna technology may have addressed similar issues in the past.

Unanswered Questions

== How does the asymmetric build-up layer count impact the overall performance of the semiconductor package? The patent application mentions that the asymmetric build-up layer count can reduce fabrication costs, but it does not delve into how this affects the functionality or reliability of the package.

== What specific materials and processes are used in the fabrication of the coreless semiconductor package? The patent application provides a general overview of the fabrication process, but it does not detail the specific materials or techniques employed in creating the package.


Original Abstract Submitted

In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.