18533369. PROGRAMMABLE PROCESSING ARRAY SUPPORTING MULTI-DIMENSIONAL INTERPOLATION COMPUTATIONS simplified abstract (Intel Corporation)

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PROGRAMMABLE PROCESSING ARRAY SUPPORTING MULTI-DIMENSIONAL INTERPOLATION COMPUTATIONS

Organization Name

Intel Corporation

Inventor(s)

Zoran Zivkovic of Hertogenbosch (NL)

Jian-Guo Chen of Basking Ridge NJ (US)

Jay Oneill of Nesquehoning PA (US)

Joseph Williams of Holmdel NJ (US)

PROGRAMMABLE PROCESSING ARRAY SUPPORTING MULTI-DIMENSIONAL INTERPOLATION COMPUTATIONS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18533369 titled 'PROGRAMMABLE PROCESSING ARRAY SUPPORTING MULTI-DIMENSIONAL INTERPOLATION COMPUTATIONS

Simplified Explanation

The abstract describes a programmable processor architecture that enables data interpolation using a fused SIMD instruction. The architecture iteratively processes portions of a look-up table (LUT) to map data sample values in a data array for interpolation.

  • The architecture enables data interpolation using a fused single instruction stream, multiple data streams (SIMD) instruction.
  • The look-up table (LUT) contains segment entries corresponding to function results evaluated with index values.
  • Index values map data sample values in a data array to segment entries for interpolation.
  • The iterative process of mapping data samples to valid segment entries in each LUT portion facilitates scaling to support larger LUTs and enables linear interpolation on multiple dimensions.

Potential Applications

This technology could be applied in:

  • Image processing for enhancing image quality through interpolation.
  • Signal processing for improving signal accuracy by interpolating data points.

Problems Solved

  • Efficient data interpolation on large look-up tables.
  • Scalability to support linear interpolation on multiple dimensions.

Benefits

  • Improved accuracy in data interpolation.
  • Enhanced performance in processing large data sets.

Potential Commercial Applications

Optimized for:

  • Graphics processing units (GPUs) for high-performance computing applications.

Possible Prior Art

One possible prior art could be the use of SIMD instructions in processor architectures for parallel processing tasks.

Unanswered Questions

1. How does the architecture handle edge cases or boundary conditions during data interpolation? 2. What are the limitations of the iterative process in mapping data samples to segment entries in large LUTs?


Original Abstract Submitted

Techniques are disclosed for a programmable processor architecture that enables data interpolation using an architecture that iteratively processes portions of a look-up table (LUT) in accordance with a fused single instruction stream, multiple data streams (SIMD) instruction. The LUT may contain segment entries that correspond to a result of evaluating a function using a corresponding index values, which represent an independent variable of the function. The index values are used to map data sample values in a data array that is to be interpolated to the segment entries. By using an iterative process of mapping data samples to valid segment entries contained in each LUT portion, the architecture advantageously facilitates scaling to support larger LUTs and thus may be expanded to enable linear interpolation on multiple dimensions.

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