18533281. MEMORY MANAGEMENT METHOD FOR SECURITY AND ELECTRONIC DEVICE THEREFOR simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
- 1 MEMORY MANAGEMENT METHOD FOR SECURITY AND ELECTRONIC DEVICE THEREFOR
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MEMORY MANAGEMENT METHOD FOR SECURITY AND ELECTRONIC DEVICE THEREFOR - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
MEMORY MANAGEMENT METHOD FOR SECURITY AND ELECTRONIC DEVICE THEREFOR
Organization Name
Inventor(s)
MEMORY MANAGEMENT METHOD FOR SECURITY AND ELECTRONIC DEVICE THEREFOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 18533281 titled 'MEMORY MANAGEMENT METHOD FOR SECURITY AND ELECTRONIC DEVICE THEREFOR
Simplified Explanation
The patent application describes an electronic device that can identify and restore defective memory addresses using a hypervisor.
- The electronic device includes at least one processor and memory connected to the processor.
- The device obtains at least one address for a memory area from a kernel and stores it in a second memory area accessible through a hypervisor.
- It identifies whether the obtained address is defective based on addresses stored in the kernel stack.
- If a defect is found, the device restores the defective address using addresses stored in the second memory area.
Potential Applications
This technology could be applied in:
- Data centers
- Cloud computing environments
Problems Solved
This technology addresses the issue of defective memory addresses in electronic devices.
Benefits
- Improved memory management
- Enhanced system reliability
Potential Commercial Applications
Optimized Memory Management in Electronic Devices
Possible Prior Art
Prior art related to memory management techniques in electronic devices may exist, but specific examples are not provided in the abstract.
Unanswered Questions
How does this technology impact system performance?
The abstract does not mention the potential impact of this technology on the overall performance of the electronic device.
Are there any limitations to the identification and restoration process?
It is not clear from the abstract if there are any limitations or challenges associated with identifying and restoring defective memory addresses.
Original Abstract Submitted
According to various embodiments, an electronic device comprises: at least one processor; and memory operatively connected to the at least one processor, wherein the memory may store instructions which, when executed by the at least one processor, cause the electronic device to: obtain, from a kernel, at least one address for a first memory area accessible through the kernel; store the at least one address in a second memory area accessible through a hypervisor; based on obtaining an address stored in a kernel stack from the kernel, identify whether the obtained address is defective, on the basis of the at least one stored address; and restore the defective address using at least one address stored in the second memory area in response to identifying the defect in the address.
