18526084. Low-K Gate Spacer and Methods for Forming the Same simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

Low-K Gate Spacer and Methods for Forming the Same

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Wen-Kai Lin of Yilan (TW)

Bo-Yu Lai of Taipei City (TW)

Li Chun Te of Renwu Township (TW)

Kai-Hsuan Lee of Hsinchu (TW)

Sai-Hooi Yeong of Zhubei City (TW)

Tien-I Bao of Taoyuan City (TW)

Wei-Ken Lin of Tainan City (TW)

Low-K Gate Spacer and Methods for Forming the Same - A simplified explanation of the abstract

This abstract first appeared for US patent application 18526084 titled 'Low-K Gate Spacer and Methods for Forming the Same

Simplified Explanation

Embodiments of the present disclosure relate to a FinFET device with gate spacers designed to reduce capacitance, formed by depositing different materials at different times during processing.

• The gate spacers in the FinFET device are formed by two or more depositions of materials to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Potential Applications

• Semiconductor manufacturing
• Integrated circuits
• Electronics industry

Problems Solved

• Reduced parasitic capacitance
• Improved performance of FinFET devices
• Enhanced efficiency of electronic devices

Benefits

• Higher performance
• Lower power consumption
• Improved reliability

SEO Optimized Title: Commercial Applications of FinFET Device with Reduced Capacitance Gate Spacers

• Mobile devices
• Computers
• Automotive electronics

Possible Prior Art

No prior art known at this time.

Unanswered Questions

How does the deposition of different materials at different times reduce parasitic capacitance in the FinFET device?

The abstract mentions that the gate spacers are formed by depositing first and second materials at different times during processing to reduce parasitic capacitance. However, it does not provide specific details on the mechanism behind this reduction.

What specific materials are used in the gate spacers to achieve reduced capacitance in the FinFET device?

While the abstract mentions that two or more materials are deposited to form the gate spacers, it does not specify the exact materials used or their properties that contribute to reducing capacitance.

Original Abstract Submitted

Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.