18522271. SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Chen-Hua Yu of Hsinchu City (TW)
Chun-Hui Yu of Hsinchu County (TW)
Kuo-Chung Yee of Taoyuan City (TW)
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18522271 titled 'SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
Simplified Explanation
The semiconductor package described in the abstract includes a chip with conductive posts, a redistribution structure with multiple layers, and first under-ball metallurgies patterns. The chip has conductive posts exposed at an active surface, while the redistribution structure is placed on top of the active surface, consisting of dielectric layers, metallization layers, and contact pads. The first under-ball metallurgies patterns are located on the contact pads, extending to contact sidewalls and top surfaces.
- Chip with conductive posts exposed at an active surface
- Redistribution structure with multiple layers including dielectric and metallization layers
- First under-ball metallurgies patterns on contact pads extending to sidewalls and top surfaces
Potential Applications
The technology described in this patent application could be applied in the semiconductor industry for packaging chips in electronic devices, such as smartphones, computers, and IoT devices.
Problems Solved
This technology solves the problem of efficiently connecting and routing electrical signals between the chip and external components in a semiconductor package.
Benefits
The benefits of this technology include improved electrical connectivity, enhanced signal routing capabilities, and potentially increased performance and reliability of semiconductor packages.
Potential Commercial Applications
The potential commercial applications of this technology could be in the manufacturing of advanced electronic devices, where high-performance semiconductor packages are required for efficient operation.
Possible Prior Art
One possible prior art for this technology could be the use of similar redistribution structures and under-ball metallurgies patterns in semiconductor packaging processes.
Unanswered Questions
How does this technology compare to existing semiconductor packaging methods?
This article does not provide a direct comparison to existing semiconductor packaging methods, leaving the reader to wonder about the specific advantages and differences between this technology and current practices.
What are the specific materials used in the fabrication of the redistribution structure and under-ball metallurgies patterns?
The article does not delve into the specific materials used in the fabrication process, leaving a gap in understanding the composition and properties of the components mentioned.
Original Abstract Submitted
A semiconductor package includes a chip, a redistribution structure, and first under- ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads.
