18521584. FINFET STRUCTURE AND METHOD WITH REDUCED FIN BUCKLING simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
- 1 FINFET STRUCTURE AND METHOD WITH REDUCED FIN BUCKLING
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 FINFET STRUCTURE AND METHOD WITH REDUCED FIN BUCKLING - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
FINFET STRUCTURE AND METHOD WITH REDUCED FIN BUCKLING
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Wei-Jen Lai of Keelung City (TW)
Yen-Ming Chen of Hsin-Chu County (TW)
Tsung-Lin Lee of Hsinchu City (TW)
FINFET STRUCTURE AND METHOD WITH REDUCED FIN BUCKLING - A simplified explanation of the abstract
This abstract first appeared for US patent application 18521584 titled 'FINFET STRUCTURE AND METHOD WITH REDUCED FIN BUCKLING
Simplified Explanation
The present disclosure describes a method for making a semiconductor structure by forming a composite stress layer on a semiconductor substrate and patterning the substrate to form fin active regions using the composite stress layer as an etch mask.
- Explanation of the patent/innovation:
* The method involves forming a composite stress layer on a semiconductor substrate. * The composite stress layer includes a first stress layer of a dielectric material with a first compressive stress and a second stress layer of the dielectric material with a second compressive stress on top of the first stress layer. * The second compressive stress is greater than the first compressive stress. * The semiconductor substrate is then patterned to form fin active regions using the composite stress layer as an etch mask.
Potential Applications
The technology described in this patent application could be applied in the semiconductor industry for the manufacturing of advanced semiconductor devices with improved performance and reliability.
Problems Solved
This technology helps in enhancing the structural integrity and performance of semiconductor devices by providing a method for forming fin active regions with precise dimensions and controlled stress levels.
Benefits
The benefits of this technology include improved device performance, increased reliability, and enhanced process control in semiconductor manufacturing.
Potential Commercial Applications
One potential commercial application of this technology could be in the production of high-performance integrated circuits for various electronic devices, such as smartphones, computers, and IoT devices.
Possible Prior Art
One possible prior art for this technology could be the use of stress engineering techniques in semiconductor manufacturing to improve device performance and reliability.
Unanswered Questions
How does this technology compare to existing methods for stress engineering in semiconductor manufacturing?
This article does not provide a direct comparison to existing methods for stress engineering in semiconductor manufacturing.
What are the specific semiconductor devices that could benefit the most from this technology?
This article does not specify the specific semiconductor devices that could benefit the most from this technology.
Original Abstract Submitted
The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.
