18520971. PACKAGE STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

PACKAGE STRUCTURE

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Chia-Kuei Hsu of Hsinchu City (TW)

Ming-Chih Yew of Hsinchu City (TW)

Shu-Shen Yeh of Taoyuan City (TW)

Che-Chia Yang of Taipei City (TW)

Po-Yao Lin of Zhudong Township Hsinchu County (TW)

Shin-Puu Jeng of Po-Shan Village (TW)

PACKAGE STRUCTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18520971 titled 'PACKAGE STRUCTURE

Simplified Explanation

The package structure described in the patent application includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. The conductive via is narrower than the first under bump metallurgy structure in a first horizontal direction, and the first under bump metallurgy structure is narrower than the first conductive pad.

• First conductive pad in a first insulating layer
• Conductive via in a second insulating layer directly under the first conductive pad
• First under bump metallurgy structure directly under the first conductive via
• Conductive via is narrower than the first under bump metallurgy structure in a first horizontal direction
• First under bump metallurgy structure is narrower than the first conductive pad

Potential Applications

The technology described in this patent application could be applied in the semiconductor industry for advanced packaging solutions.

Problems Solved

This technology solves the problem of optimizing the package structure for better performance and reliability in semiconductor devices.

Benefits

The benefits of this technology include improved electrical connectivity, enhanced thermal management, and overall increased efficiency in semiconductor packaging.

Potential Commercial Applications

• "Innovative Package Structure for Enhanced Semiconductor Devices"

Possible Prior Art

There may be prior art related to package structures in semiconductor devices, but specific examples are not provided in this patent application.

Unanswered Questions

How does this package structure compare to existing solutions in terms of cost-effectiveness?

The cost-effectiveness of implementing this package structure compared to existing solutions is not addressed in the patent application.

What impact does this package structure have on the overall size of the semiconductor device?

The impact of this package structure on the size of the semiconductor device is not discussed in detail in the patent application.

Original Abstract Submitted

A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.