18518790. CHIP PACKAGE STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
CHIP PACKAGE STRUCTURE
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Ling-Wei Li of Hsinchu City (TW)
Jung-Hua Chang of Hsinchu (TW)
Cheng-Lin Huang of Hsinchu City (TW)
CHIP PACKAGE STRUCTURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18518790 titled 'CHIP PACKAGE STRUCTURE
Simplified Explanation
The chip package structure described in the patent application includes a first substrate with a conductive via structure, a barrier layer, an insulating layer, a conductive pad, a conductive bump, and a second substrate with an underfill layer.
- The chip package structure has a conductive via structure passing through the first substrate.
- A barrier layer is present over the surface of the first substrate.
- An insulating layer is placed over the barrier layer.
- A conductive pad is located over the insulating layer, with a portion passing through the insulating layer and the barrier layer to connect to the conductive via structure.
- A conductive bump is positioned over the conductive pad.
- The chip package structure includes a second substrate and an underfill layer between the first and second substrates.
Potential Applications
- Semiconductor packaging
- Integrated circuits
- Electronic devices
Problems Solved
- Improving electrical connections in chip packages
- Enhancing signal transmission efficiency
- Increasing reliability of electronic components
Benefits
- Enhanced performance of electronic devices
- Improved durability of chip packages
- Higher quality connections for integrated circuits
Original Abstract Submitted
A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer. The conductive pad has a first portion passing through the insulating layer and the barrier layer and connected to the conductive via structure. The chip package structure includes a conductive bump over the conductive pad. The chip package structure includes a second substrate. The chip package structure includes an underfill layer between the first substrate and the second substrate.
