18518591. SEMICONDUCTOR PACKAGE UTILIZING A HYBRID BONDING PROCESS AND METHOD OF MANUFACTURING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE UTILIZING A HYBRID BONDING PROCESS AND METHOD OF MANUFACTURING THE SAME
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE UTILIZING A HYBRID BONDING PROCESS AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18518591 titled 'SEMICONDUCTOR PACKAGE UTILIZING A HYBRID BONDING PROCESS AND METHOD OF MANUFACTURING THE SAME
Simplified Explanation
The semiconductor package described in the patent application includes two semiconductor chips, with the second chip being directly connected to the first chip. The second chip has an overhang that protrudes from the bonding region, which helps prevent bonding failures that could be caused by particles adhering to the edge of the second chip.
- First semiconductor chip with a groove in the peripheral region and a higher bonding region
- Second semiconductor chip placed in the bonding region of the first chip
- Direct electrical connection between the first and second semiconductor chips
- Overhang on the second chip spaced apart from the bottom surface of the groove to avoid bonding failures
Potential Applications
- Semiconductor manufacturing
- Electronics industry
- Integrated circuits
Problems Solved
- Bonding failures caused by particles during wafer cutting
- Ensuring secure electrical connection between semiconductor chips
Benefits
- Improved reliability of semiconductor packages
- Enhanced performance of electronic devices
- Cost-effective manufacturing process
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a peripheral region having a groove and a bonding region that is disposed higher than the groove. The second semiconductor chip is disposed in the bonding region of the first semiconductor chip. The second semiconductor chip is directly electrically connected to the first semiconductor chip. The second semiconductor chip includes an overhang protruded from the bonding region. The overhang is spaced apart from a bottom surface of the groove. Thus, a bonding failure, which may be caused by particles generated during a cutting the wafer and adhered to the edge portion of the second semiconductor chip, between the first semiconductor chip and the second semiconductor chip might be avoided.
