18517489. Stacking Via Structures for Stress Reduction simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

Stacking Via Structures for Stress Reduction

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Shu-Shen Yeh of Taoyuan City (TW)

Che-Chia Yang of Taipei City (TW)

Chin-Hua Wang of New Taipei City (TW)

Po-Yao Lin of Zhudong Township (TW)

Shin-Puu Jeng of Hsinchu (TW)

Chia-Hsiang Lin of Zhubei City (TW)

Stacking Via Structures for Stress Reduction - A simplified explanation of the abstract

This abstract first appeared for US patent application 18517489 titled 'Stacking Via Structures for Stress Reduction

Simplified Explanation

The method involves forming layers and structures in a semiconductor device, including redistribution lines, vias, and bumps, with specific offsets between them.

• Form a first dielectric layer.
• Create a first redistribution line with a via and trace.
• Add a second dielectric layer covering the redistribution line.
• Pattern the second dielectric layer to create a via opening.
• Form a second via and a conductive pad over it.
• Place a conductive bump on the pad, with a center offset.
• Offset the second via from the center of the conductive bump.

Potential Applications

• Semiconductor manufacturing
• Integrated circuit design
• Microelectronics

Problems Solved

• Improved signal routing
• Enhanced electrical connections
• Increased device reliability

Benefits

• Higher performance
• Better signal integrity
• More compact designs

Original Abstract Submitted

A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.