18517400. INTEGRATED CIRCUIT FIN STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

INTEGRATED CIRCUIT FIN STRUCTURE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Po-Hsiang Huang of Hsinchu (TW)

Fong-Yuan Chang of Hsinchu (TW)

Clement Hsingjen Wann of Hsinchu (TW)

Chih-Hsin Ko of Hsinchu (TW)

Sheng-Hsiung Chen of Hsinchu (TW)

Li-Chun Tien of Hsinchu (TW)

Chia-Ming Hsu of Hsinchu (TW)

INTEGRATED CIRCUIT FIN STRUCTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18517400 titled 'INTEGRATED CIRCUIT FIN STRUCTURE

Simplified Explanation

The patent application describes an IC device with rows of fin field-effect transistors (FinFETs) where the second row is positioned between and adjacent to the first and third rows. The FinFETs in the first row are either n-type or p-type, while the FinFETs in the second and third rows are the opposite type. The first and third rows have a certain number of fins, while the second row has one more or one fewer fin than the first and third rows.

• IC device with rows of FinFETs
• Second row positioned between and adjacent to first and third rows
• First row FinFETs are n-type or p-type
• Second and third row FinFETs are the opposite type
• First and third rows have a specific number of fins
• Second row has one more or one fewer fin than the first and third rows

Potential Applications

• Semiconductor manufacturing
• Integrated circuit design
• Electronics industry

Problems Solved

• Efficient use of space in IC devices
• Optimization of transistor configurations
• Enhanced performance of FinFETs

Benefits

• Improved transistor density
• Enhanced circuit performance
• Increased efficiency in IC design

Original Abstract Submitted

An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.