18517017. LOW POWER CLOCK NETWORK simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
LOW POWER CLOCK NETWORK
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
LOW POWER CLOCK NETWORK - A simplified explanation of the abstract
This abstract first appeared for US patent application 18517017 titled 'LOW POWER CLOCK NETWORK
Simplified Explanation
In this patent application, a method is described for generating a second clock signal with a lower frequency than a reference clock signal, and propagating it through a clock tree to provide to a component of an integrated circuit.
- A first clock signal is generated from a reference clock signal.
- The first clock signal has a lower frequency than the reference clock signal.
- The first clock signal is sent through a clock tree towards a component of an integrated circuit.
- At the terminal point of the clock tree, a second clock signal with a second frequency is generated from the first clock signal.
- The second clock signal is then provided to the component of the integrated circuit.
Potential Applications
- Integrated circuits
- Clock signal generation
- Frequency division
Problems Solved
- Efficient clock signal distribution
- Frequency control in integrated circuits
Benefits
- Lower power consumption
- Improved performance in integrated circuits
- Precise clock signal distribution
Original Abstract Submitted
A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.
