18516971. SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Shin-Yi Yang of New Taipei (TW)
SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18516971 titled 'SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME
Simplified Explanation
The method described in the abstract involves forming a semiconductor package by providing two integrated circuit dies with different circuit designs on a substrate, connecting power rails and lines, and forming interconnect structures on the surfaces of the dies.
- Two integrated circuit dies with separate circuit designs are placed on a substrate.
- Power rails are extended from one die to the other, connecting to a source/drain feature.
- Power lines are formed through the entire thickness of both dies.
- Interconnect structures are created on the surfaces of both dies.
Potential Applications
- Semiconductor manufacturing
- Electronics industry
- Integrated circuit packaging
Problems Solved
- Efficient power distribution in semiconductor packages
- Integration of multiple circuit designs on a single substrate
Benefits
- Cost-effective semiconductor packaging
- Improved power distribution efficiency
- Enhanced circuit design flexibility
Original Abstract Submitted
Embodiments of the present disclosure provide a method for forming a semiconductor package. In one embodiment, the method includes providing a first integrated circuit die having a first circuit design on a substrate, providing a second integrated circuit die having a second circuit design on the substrate, wherein the first and second integrated circuit dies are separated from each other by a scribe line. The method also includes forming a first interconnect structure on a first surface of the first integrated circuit die, forming a second interconnect structure on a first surface of the second integrated circuit die, extending a power rail from a second surface of the first integrated circuit die to a first side of a source/drain (S/D) feature, forming one or more power lines through an entire thickness of the first and second integrated circuit dies, respectively, forming a third interconnect structure on the second surface of the first integrated circuit die, and forming a fourth interconnect structure on the second surface of the second integrated circuit die.
