18516408. Fin Loss Prevention simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

Fin Loss Prevention

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Hung-Ju Chou of Taipei City (TW)

Chih-Chung Chang of Nantou-County (TW)

Jun-Ming Kuo of Taipei City (TW)

Che-Yuan Hsu of Hsinchu City (TW)

Pei-Ling Kao of Hsichu (TW)

Chen-Hsuan Liao of Hsinchu (TW)

Fin Loss Prevention - A simplified explanation of the abstract

This abstract first appeared for US patent application 18516408 titled 'Fin Loss Prevention

Simplified Explanation

The method described in the patent application is for reducing fin oxidation during the formation of fin isolation regions in a semiconductor substrate.

• Provides a semiconductor substrate with an n-doped region and a p-doped region
• Epitaxially grows different layers on the n-doped and p-doped regions
• Forms thinner third layer on top surfaces of the first and second layers
• Etches the layers to form fin structures and isolation regions between them

Potential Applications

• Semiconductor manufacturing
• Integrated circuit fabrication

Problems Solved

• Reducing fin oxidation during formation
• Improving fin isolation in semiconductor devices

Benefits

• Enhanced performance of semiconductor devices
• Increased reliability of integrated circuits
• Improved manufacturing efficiency

Original Abstract Submitted

The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.