18516215. Gate Structures For Semiconductor Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
Gate Structures For Semiconductor Devices
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Chung-Liang Cheng of Changhua County (TW)
Huang-Lin Chao of Hillsboro OR (US)
Gate Structures For Semiconductor Devices - A simplified explanation of the abstract
This abstract first appeared for US patent application 18516215 titled 'Gate Structures For Semiconductor Devices
Simplified Explanation
The abstract describes a semiconductor device with gate structures designed to achieve ultra-low threshold voltages, along with a method of fabricating the device.
- Formation of nanostructured channel regions in nanostructured layers
- Creation of gate-all-around (GAA) structures surrounding the channel regions
- Selective formation of Al-based n-type work function metal layer and Si-based capping layer
- Deposition of bi-layer of Al-free p-type work function metal layers
- Addition of fluorine blocking layer
- Deposition of gate metal fill layer
Potential Applications
- High-performance electronic devices
- Low-power consumption applications
- Advanced computing systems
Problems Solved
- Achieving ultra-low threshold voltages
- Enhancing device performance
- Improving energy efficiency
Benefits
- Increased efficiency in semiconductor devices
- Enhanced performance capabilities
- Potential for new technological advancements
Original Abstract Submitted
The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.
