18516143. BUFFER CONTROL OF MULTIPLE MEMORY BANKS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

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BUFFER CONTROL OF MULTIPLE MEMORY BANKS

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Shih-Lien Linus Lu of Hsinchu (TW)

BUFFER CONTROL OF MULTIPLE MEMORY BANKS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18516143 titled 'BUFFER CONTROL OF MULTIPLE MEMORY BANKS

Simplified Explanation

The patent application abstract describes a memory system with memory banks and buffers, where each buffer can write data to a corresponding memory bank. The system includes a buffer controller with a queue register, first pointer register, second pointer register, and queue controller.

  • The queue register stores addresses of memory banks.
  • The first pointer register predicts the memory bank where the next write process will be completed.
  • The second pointer register indicates the entry to be updated.
  • The queue controller configures the queue register based on the first and second pointer registers, and configures buffers to perform write processes according to the entries.

Potential Applications

This technology could be applied in computer systems, data storage devices, and other electronic devices that require efficient memory management and data writing processes.

Problems Solved

1. Efficient memory bank utilization. 2. Streamlined data writing processes. 3. Improved memory system performance.

Benefits

1. Faster data writing speeds. 2. Enhanced memory system efficiency. 3. Optimized memory bank usage.


Original Abstract Submitted

Disclosed herein are related to operating a memory system including memory banks and buffers. Each buffer may perform a write process to write data to a corresponding memory bank. In one aspect, the memory system includes a buffer controller including a queue register, a first pointer register, a second pointer register, and a queue controller. In one aspect, the queue register includes entries, where each entry may store an address of a corresponding memory bank. The first pointer register may indicate a first entry storing an address of a memory bank, on which the write process is predicted to be completed next. The second pointer register may indicate a second entry to be updated. The queue controller may configure the queue register according to the first pointer register and the second pointer register, and configure one or more buffers to perform the write process, according to the entries.

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