18515908. METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Shahaji B. More of Hsinchu City (TW)

Chun Hsiung Tsai of Xinpu Township (TW)

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18515908 titled 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Simplified Explanation

The abstract describes a method of manufacturing a semiconductor device involving the formation of an upper fin structure with alternating semiconductor layers, the creation of a sacrificial gate structure, etching of the source/drain region, formation of inner spacers, and the deposition of a source/drain epitaxial layer.

• Upper fin structure with alternating semiconductor layers and sacrificial gate structure are formed.
• Source/drain region of upper fin structure is etched to create a source/drain space.
• First semiconductor layers are laterally etched through the source/drain space.
• Inner spacers made of dielectric material are formed on the etched first semiconductor layers.
• Source/drain epitaxial layer is deposited in the source/drain space to cover the inner spacers.
• Part of the lower fin structure is etched to form a recess exposing a (111) surface.

Potential Applications

• Semiconductor manufacturing industry
• Advanced electronic devices

Problems Solved

• Enhanced performance of semiconductor devices
• Improved integration of components

Benefits

• Increased efficiency in manufacturing process
• Higher functionality of semiconductor devices

Original Abstract Submitted

In a method of manufacturing a semiconductor device, an upper fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a lower fin structure, a sacrificial gate structure is formed over the upper fin structure, a source/drain region of the upper fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, an inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers, and a source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. In etching the source/drain region, a part of the lower fin structure is also etched to form a recess, in which a (111) surface is exposed.