18515523. METHOD FOR IMPROVING CONTROL GATE UNIFORMITY DURING MANUFACTURE OF PROCESSORS WITH EMBEDDED FLASH MEMORY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
- 1 METHOD FOR IMPROVING CONTROL GATE UNIFORMITY DURING MANUFACTURE OF PROCESSORS WITH EMBEDDED FLASH MEMORY
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 METHOD FOR IMPROVING CONTROL GATE UNIFORMITY DURING MANUFACTURE OF PROCESSORS WITH EMBEDDED FLASH MEMORY - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Original Abstract Submitted
METHOD FOR IMPROVING CONTROL GATE UNIFORMITY DURING MANUFACTURE OF PROCESSORS WITH EMBEDDED FLASH MEMORY
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
METHOD FOR IMPROVING CONTROL GATE UNIFORMITY DURING MANUFACTURE OF PROCESSORS WITH EMBEDDED FLASH MEMORY - A simplified explanation of the abstract
This abstract first appeared for US patent application 18515523 titled 'METHOD FOR IMPROVING CONTROL GATE UNIFORMITY DURING MANUFACTURE OF PROCESSORS WITH EMBEDDED FLASH MEMORY
Simplified Explanation
The method described in the abstract involves planarizing a protective layer over gate materials in a recessed region on a substrate. This process includes forming a first planarized surface by planarizing a sacrificial layer over the protective layer, and then forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer evenly across the recessed region. An etch mask layer is then formed over the second planarized surface, and control gate stacks are created in the recessed region by etching the gate materials.
- Planarizing protective layer over gate materials in a recessed region
- Forming first planarized surface by planarizing sacrificial layer
- Creating second planarized surface of protective layer by etching sacrificial layer
- Forming etch mask layer over second planarized surface
- Creating control gate stacks in recessed region by etching gate materials
Potential Applications
- Semiconductor manufacturing - Integrated circuit fabrication - Nanotechnology research
Problems Solved
- Ensuring uniformity in gate stack formation - Improving overall device performance - Enhancing reliability of semiconductor devices
Benefits
- Increased efficiency in manufacturing process - Improved device functionality - Enhanced quality control in semiconductor production
Original Abstract Submitted
A method includes planarizing a protective layer over gate materials overlying a recessed region in a substrate. The planarizing includes forming a first planarized surface by planarizing a sacrificial layer over the protective layer, and forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer at an even rate across the recessed region. An etch mask layer is formed over the second planarized surface, and control gate stacks are formed in the recessed region by etching the gate materials.
