18515148. SEMICONDUCTOR DEVICE HAVING 2D CHANNEL LAYER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

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SEMICONDUCTOR DEVICE HAVING 2D CHANNEL LAYER

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Yun-Yuan Wang of Kaohsiung City (TW)

Chih-Hsiang Hsiao of Taoyuan City (TW)

I-Chih Ni of New Taipei City (TW)

Chih-I Wu of Taipei City (TW)

SEMICONDUCTOR DEVICE HAVING 2D CHANNEL LAYER - A simplified explanation of the abstract

This abstract first appeared for US patent application 18515148 titled 'SEMICONDUCTOR DEVICE HAVING 2D CHANNEL LAYER

Simplified Explanation

The patent application describes a device with a chalcogenide channel layer, a chalcogenide barrier layer, source/drain contacts, and a gate electrode.

  • The chalcogenide channel layer is positioned on top of the substrate.
  • The chalcogenide barrier layer is placed over the chalcogenide channel layer.
  • The dopant concentration of the chalcogenide barrier layer is higher than that of the chalcogenide channel layer.
  • The source/drain contacts are located on the chalcogenide channel layer.
  • The gate electrode is positioned over the substrate.

Potential Applications

  • Semiconductor devices
  • Memory storage devices
  • Logic circuits

Problems Solved

  • Improved performance of semiconductor devices
  • Enhanced memory storage capabilities
  • Increased efficiency of logic circuits

Benefits

  • Higher dopant concentration in the barrier layer improves device performance
  • Optimal positioning of layers enhances overall functionality
  • Increased reliability and durability of the device


Original Abstract Submitted

A device includes a substrate, a chalcogenide channel layer, a chalcogenide barrier layer, source/drain contacts, and a gate electrode. The chalcogenide channel layer is over the substrate. The chalcogenide barrier layer is over the chalcogenide channel layer. A dopant concentration of the chalcogenide barrier layer is greater than a dopant concentration of the chalcogenide channel layer. The source/drain contacts are over the chalcogenide channel layer. The gate electrode is over the substrate.