18514254. MULTI-METAL FILL WITH SELF-ALIGNED PATTERNING AND DIELECTRIC WITH VOIDS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
MULTI-METAL FILL WITH SELF-ALIGNED PATTERNING AND DIELECTRIC WITH VOIDS
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Tai-I Yang of Hsinchu City (TW)
Wei-Chen Chu of Taichung City (TW)
Hsiang-Wei Liu of Tainan City (TW)
Li-Lin Su of Taichung County (TW)
Yung-Hsu Wu of Taipei City (TW)
MULTI-METAL FILL WITH SELF-ALIGNED PATTERNING AND DIELECTRIC WITH VOIDS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18514254 titled 'MULTI-METAL FILL WITH SELF-ALIGNED PATTERNING AND DIELECTRIC WITH VOIDS
Simplified Explanation
The patent application discloses an interconnect formation process that utilizes a patterning photolithography/etch process with self-aligned interconnects to improve photolithography overlay (OVL) margin and support multi-metal gap fill and low-k dielectric formation with voids.
- The interconnect formation process employs a wider pattern for alignment, improving photolithography overlay margin.
- The process enables self-aligned interconnects, reducing overlay errors and patterning defects.
- Supports multi-metal gap fill and low-k dielectric formation with voids, enhancing overall device performance.
Potential Applications
The technology can be applied in semiconductor manufacturing for advanced interconnect formation processes.
Problems Solved
1. Reduction of photolithography overlay errors. 2. Improved patterning accuracy and defect reduction. 3. Support for multi-metal gap fill and low-k dielectric formation with voids.
Benefits
1. Increased wafer yield. 2. Enhanced device performance. 3. Improved alignment accuracy in patterning processes.
Original Abstract Submitted
Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
