18513968. MRAM DEVICE HAVING SELF-ALIGNED SHUNTING LAYER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
MRAM DEVICE HAVING SELF-ALIGNED SHUNTING LAYER
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
William J. Gallagher of Hsinchu (TW)
Shy-Jay Lin of Jhudong Township (TW)
Ming Yuan Song of Hsinchu City (TW)
MRAM DEVICE HAVING SELF-ALIGNED SHUNTING LAYER - A simplified explanation of the abstract
This abstract first appeared for US patent application 18513968 titled 'MRAM DEVICE HAVING SELF-ALIGNED SHUNTING LAYER
Simplified Explanation
The semiconductor structure described in the patent application includes a memory cell overlying a substrate, with a lower via positioned underneath the memory cell. A first conductive layer made of a first material is located vertically between the memory cell and the lower via, extending along a lateral distance. A second conductive layer, made of a different material from the first, covers the upper surface of the first conductive layer and aligns with the bottom surface of the memory cell.
- Memory cell overlying a substrate
- Lower via positioned underneath the memory cell
- First conductive layer vertically between the memory cell and the lower via
- Second conductive layer covering the upper surface of the first conductive layer
- Second conductive layer made of a different material from the first conductive layer
- Second conductive layer aligns with the bottom surface of the memory cell
Potential Applications
- Semiconductor manufacturing
- Memory cell technology
- Integrated circuit design
Problems Solved
- Efficient memory cell layout
- Improved vertical and lateral connectivity
- Enhanced semiconductor structure performance
Benefits
- Higher memory cell density
- Enhanced electrical conductivity
- Improved overall semiconductor structure efficiency
Original Abstract Submitted
Various embodiments of the present disclosure are directed towards a semiconductor structure including a memory cell overlying a substrate. A lower via underlies the memory cell. The lower via is laterally offset from the memory cell by a lateral distance. A first conductive layer is disposed vertically between the memory cell and the lower via and comprising a first material. The first conductive layer continuously extends along the lateral distance. A second conductive layer extends across an upper surface of the first conductive layer and comprises a second material different from the first material. A bottom surface of the second conductive layer is aligned with a bottom surface of the memory cell.
