18513730. MEMORY DEVICE, A CONTROLLER FOR CONTROLLING THE SAME, A MEMORY SYSTEM INCLUDING THE SAME, AND AN OPERATING METHOD OF THE SAME simplified abstract (Samsung Electronics Co., Ltd.)

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MEMORY DEVICE, A CONTROLLER FOR CONTROLLING THE SAME, A MEMORY SYSTEM INCLUDING THE SAME, AND AN OPERATING METHOD OF THE SAME

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Yesin Ryu of Seoul (KR)

Sunggi Ahn of Jinju-si (KR)

Jaeyoun Youn of Seoul (KR)

MEMORY DEVICE, A CONTROLLER FOR CONTROLLING THE SAME, A MEMORY SYSTEM INCLUDING THE SAME, AND AN OPERATING METHOD OF THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18513730 titled 'MEMORY DEVICE, A CONTROLLER FOR CONTROLLING THE SAME, A MEMORY SYSTEM INCLUDING THE SAME, AND AN OPERATING METHOD OF THE SAME

Simplified Explanation

The memory device described in the abstract includes a memory cell array, an error correction circuit, and an error check and scrub (ECS) circuit. The ECS circuit is responsible for performing a scrubbing operation on the memory cell array, storing error addresses, and receiving page offline addresses from an external device.

  • Memory cell array with memory cells at intersections of wordlines and bitlines
  • Error correction circuit to read data from memory cell array and correct errors
  • ECS circuit for scrubbing operation, storing error addresses, and receiving page offline addresses

Potential Applications

The technology described in this patent application could be applied in:

  • Data storage systems
  • Computer memory modules
  • Embedded systems

Problems Solved

This technology helps in:

  • Detecting and correcting errors in data storage
  • Improving data reliability and integrity
  • Enhancing overall system performance

Benefits

The benefits of this technology include:

  • Increased data accuracy
  • Enhanced system reliability
  • Improved data integrity

Potential Commercial Applications

The potential commercial applications of this technology could be in:

  • Data centers
  • Cloud computing services
  • High-performance computing systems

Possible Prior Art

One possible prior art for this technology could be:

  • Error correction codes used in memory systems

Unanswered Questions

How does the ECS circuit handle multiple errors during the scrubbing operation?

The abstract does not provide details on how the ECS circuit manages multiple errors during the scrubbing operation.

What is the impact of the error correction circuit on the overall system performance?

The abstract does not mention the specific impact of the error correction circuit on the overall system performance.


Original Abstract Submitted

A memory device including: a memory cell array including a plurality of memory cells disposed at intersections of wordlines and bitlines; an error correction circuit configured to read data from the memory cell array and to correct an error in the read data; and an error check and scrub (ECS) circuit configured to perform a scrubbing operation on the memory cell array, wherein the ECS circuit includes: a first register configured to store an error address obtained in the scrubbing operation; and a second register configured to store a page offline address received from an external device.